Patents by Inventor Chi-Tsai Chen
Chi-Tsai Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10796759Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.Type: GrantFiled: May 16, 2019Date of Patent: October 6, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
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Publication number: 20190272873Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.Type: ApplicationFiled: May 16, 2019Publication date: September 5, 2019Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
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Patent number: 10311952Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.Type: GrantFiled: March 27, 2018Date of Patent: June 4, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
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Patent number: 10128313Abstract: In the present disclosure, a non-volatile memory cell comprises a data storage unit, a selection unit and a switching unit. The data storage unit is configured to store an information bit and has a first end and a second end. The first end is coupled to a bit line. The selection unit is configured to access the data storage unit, and the selection unit has a first end coupled to a select line, a second end coupled to the second end of the data storage unit, and a third end coupled to a source line. The switching unit is configured to perform a formation operation and has a first end coupled to a forming line and a second end coupled to the second end of the data storage unit.Type: GrantFiled: February 5, 2016Date of Patent: November 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Tsai Chen, Wenhsien Kuo, Meng-Chun Shih, Ching-Huang Wang, Chia-Fu Lee, Yu-Der Chih
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Publication number: 20180218770Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.Type: ApplicationFiled: March 27, 2018Publication date: August 2, 2018Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
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Patent number: 9934853Abstract: The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.Type: GrantFiled: February 6, 2017Date of Patent: April 3, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
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Publication number: 20170236581Abstract: The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.Type: ApplicationFiled: February 6, 2017Publication date: August 17, 2017Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
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Publication number: 20170229515Abstract: In the present disclosure, a non-volatile memory cell comprises a data storage unit, a selection unit and a switching unit. The data storage unit is configured to store an information bit and has a first end and a second end. The first end is coupled to a bit line. The selection unit is configured to access the data storage unit, and the selection unit has a first end coupled to a select line, a second end coupled to the second end of the data storage unit, and a third end coupled to a source line. The switching unit is configured to perform a formation operation and has a first end coupled to a forming line and a second end coupled to the second end of the data storage unit.Type: ApplicationFiled: February 5, 2016Publication date: August 10, 2017Inventors: CHI-TSAI CHEN, WENHSIEN KUO, MENG-CHUN SHIH, CHING-HUANG WANG, CHIA-FU LEE, YU-DER CHIH
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Publication number: 20150069483Abstract: A single-poly NVM cell includes a substrate having an isolation region separating a first OD region from a second OD region, a read transistor within the first OD region, and a coupling capacitor within the second OD region. A first ion well completely overlaps with the first oxide define region. The read transistor includes a drain region, a source region, a channel region, a single-poly floating gate overlying the channel region, and a gate dielectric layer between the floating gate and the channel region. The coupling capacitor includes a shallow ion well, a heavily-doped, ultra-shallow dopant region in the shallow ion well, a single-poly charge-storage floating gate overlying the heavily-doped, ultra-shallow dopant region, and a gate dielectric layer under the charge storage floating gate. The shallow ion well has a junction depth that is substantially equal to or shallower than a trench depth of the isolation region.Type: ApplicationFiled: September 9, 2014Publication date: March 12, 2015Inventor: Chi-Tsai Chen
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Patent number: 8975679Abstract: A single-poly NVM cell includes a substrate having an isolation region separating a first OD region from a second OD region, a read transistor within the first OD region, and a coupling capacitor within the second OD region. A first ion well completely overlaps with the first oxide define region. The read transistor includes a drain region, a source region, a channel region, a single-poly floating gate overlying the channel region, and a gate dielectric layer between the floating gate and the channel region. The coupling capacitor includes a shallow ion well, a heavily-doped, ultra-shallow dopant region in the shallow ion well, a single-poly charge-storage floating gate overlying the heavily-doped, ultra-shallow dopant region, and a gate dielectric layer under the charge storage floating gate. The shallow ion well has a junction depth that is substantially equal to or shallower than a trench depth of the isolation region.Type: GrantFiled: September 9, 2014Date of Patent: March 10, 2015Assignee: Gembedded Tech Ltd.Inventor: Chi-Tsai Chen