Abstract: A BEOL manufacturing process for forming a via process between two metal lines on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation of the remainder of the first metal adhesion layer and formation of a second metal adhesion layer within the patterned via hole. This process of forming the remaining portion of the first metal adhesion layer can be referred to as a wafer load, unload, load (LUL) process. By using a LUL process, thermal history is minimized, which reduces Al extrusion at the via interfaces.

Abstract: A method for symmetric deposition of metal layer over a metal layer registration key comprises using MOCVD to form the metal layer. Once the symmetric metal layer is formed, a metal layer registration key can be accurately detected and the metal layer registration key overlay shift can be improved.

Abstract: A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the first polished surface with a rinse composition to provide a rinsed surface; and polishing the rinsed surface by providing a second polishing composition to provide a second polished surface.

Abstract: A process for forming an ARC layer in the fabrication of a semiconductor device comprises forming a modified ARC layer that increases the resistance to crown defects and bridging and also provides better adhesion for the ARC layer with the underlying metal layer. The modified ARC layer can comprise two titanium nitride ARC layers, a titanium nitride/titanium/titanium nitride sandwich structure, a modified titanium nitride layer, or an extended thickness titanium nitride layer.

Abstract: A method for forming shallow trench isolation structures is disclosed. The methods include providing a substrate having an upper surface and having an opening extending down from said upper surface, providing a first dielectric layer over at least a portion of the upper surface of the substrate and filling the opening, providing a second dielectric layer over the first dielectric layer, and removing portions of the first and second dielectric layers, wherein the first dielectric layer has a higher index of refraction than the second dielectric layer.

Abstract: A BEOL manufacturing process for forming a via on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation of the remainder of the first metal adhesion layer and formation of a second metal adhesion layer within the patterned via hole. This process of forming the remaining portion of the first metal adhesion layer can be referred to as a load, unload, load (LUL) process. By using a LUL process, thermal processing is minimized, which reduces Al extrusion at the via interfaces.

Abstract: A BEOL manufacturing process for forming a via process between two metal lines on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation of the remainder of the first metal adhesion layer and formation of a second metal adhesion layer within the patterned via hole. This process of forming the remaining portion of the first metal adhesion layer can be referred to as a wafer load, unload, load (LUL) process. By using a LUL process, thermal history is minimized, which reduces Al extrusion at the via interfaces.

Abstract: A method for improving accuracy of determining polish endpoint of chemical mechanical polish (CMP) process is provided. The method is performed before the CMP process. First, a test wafer with a to-be-polished layer and a material layer under the to-be-polished layer is provided. Then, a test beam with a wavelength is provided to irradiate the test wafer. The CMP process is performed to the test wafer to remove the to-be-polished layer until the material layer is exposed while the reflection of the test beam during the polish process is continuously detected. The reflection tendency is detected when the to-be-polished layer is to be completely removed and when the CMP process reaches the interface between the to-be-polished layer and the material layer. If the reflection tendency is gradually weakened, the test beam with the wavelength is chosen for the subsequent polish process.

Abstract: A method for forming a shallow trench isolation region (STI) is disclosed. The method comprises the steps of sequentially forming a pad oxide layer and a nitride silicon layer over a provided substrate. Next, the pad oxide layer, the nitride silicon layer, and the substrate are partially etched to form a trench. An oxide liner and a nitride liner are then formed in the trench. Subsequently, a two-stage high-density plasma chemical vapor deposition process is performed to form a shallow trench isolation region.

Abstract: A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the first polished surface with a rinse composition to provide a rinsed surface; and polishing the rinsed surface by providing a second polishing composition to provide a second polished surface.

Abstract: A method for symmetric deposition of metal layer over a metal layer registration key comprises using MOCVD to form the metal layer. Once the symmetric metal layer is formed, a metal layer registration key can be accurately detected and the metal layer registration key overlay shift can be improved.

Abstract: A process for forming an ARC layer in the fabrication of a semiconductor device comprises forming a modified ARC layer that increases the resistance to crown defects and bridging and also provides better adhesion for the ARC layer with the underlying metal layer. The modified ARC layer can comprise two titanium nitride ARC layers, a titanium nitride/titanium/titanium nitride sandwich structure, a modified titanium nitride layer, or an extended thickness titanium nitride layer.

Abstract: An alignment mark is fabricated containing a mark portion and a trench structure. The trench structure surrounds the mark portion and is at a distance from the mark portion. The mark portion has a plurality of notches. Due to the erosion effect caused by the trench structure, it can prevent the residue leave in the notches of the alignment mark.

Abstract: A method for forming a semiconductor device includes providing a substrate, providing aluminum metal lines on the substrate, forming a barrier layer over the aluminum metal lines, and forming a silicon-rich dielectric layer over the barrier layer. An inter-metal dielectric (IMD) layer may be formed to cover at least a portion of the silicon-rich dielectric layer.

Abstract: A method for improving accuracy of determining polish endpoint of chemical mechanical polish (CMP) process is provided. The method is performed before the CMP process. First, a test wafer with a to-be-polished layer and a material layer under the to-be-polished layer is provided. Then, a test beam with a wavelength is provided to irradiate the test wafer. The CMP process is performed to the test wafer to remove the to-be-polished layer until the material layer is exposed while the reflection of the test beam during the polish process is continuously detected. The reflection tendency is detected when the to-be-polished layer is to be completely removed and when the CMP process reaches the interface between the to-be-polished layer and the material layer. If the reflection tendency is gradually weakened, the test beam with the wavelength is chosen for the subsequent polish process.

Abstract: A process is described for creating a uniformly thick layer of titanium, cobalt, or nickel silicide over a layer of polysilicon that has features or a non-planar topography. A dual layer of metal is deposited onto patterned polysilicon such that the first layer covers the bottoms and tops of the non-planar topography and the second layer covers the sidewalls and tops of the non-planar topography. By heating the metal, etching away any un-reacted metal, and heating the result a second time, a metal silicide layer of uniform thickness, reduced stress and reduced resistivity is formed.

Abstract: A process is described for creating a uniformly thick layer of titanium, cobalt, or nickel silicide over a layer of polysilicon that has features or a non-planar topography. A dual layer of metal is deposited onto patterned polysilicon such that the first layer covers the bottoms and tops of the non-planar topography and the second layer covers the sidewalls and tops of the non-planar topography. By heating the metal, etching away any un-reacted metal, and heating the result a second time, a metal silicide layer of uniform thickness, reduced stress and reduced resistivity is formed.

Abstract: A method and apparatus for a gas detection system comprises a sample cell containing at least one aperture and a substrate. The substrate comprises a chemiluminescent material that produces photons upon exposure to a fluorine-containing compound. A photo-detector is positioned to receive at least a portion of the photons, wherein the photo-detector generates an electrical output signal relating to a concentration of the fluorine-containing compound.

Abstract: A method for manufacturing contact plug is disclosed. A dielectric layer is formed over a substrate having a conductive region. A contact opening is formed in the dielectric layer and exposing the conductive region within the opening. A first refractory metal layer is formed over the dielectric layer, and the sidewalls and bottom of the contact opening. A first refractory metal nitride layer is formed on the first refractory metal layer. A first plasma treatment step is carried out to transform the first refractory metal nitride layer into a first metal nitrided barrier layer. A thermal-process is carried out to form metal silicide on the conductive region. A second refractory metal nitride layer is formed on the first metal nitride barrier layer. A second plasma treatment step is carried out to transform the second refractory metal nitride layer into a second metal nitrided barrier layer.

Abstract: A method for planarizing the dielectric layer of a flash memory device, wherein the method is applied on substrate of a flash memory device having a plurality of gate structures formed thereon and a protective layer is formed on the gate structures. A dielectric layer is formed on the substrate, filling the space between the gate structures and covering the protective layer. Using the protective layer as a polishing endpoint layer, a fixed base and a polishing slurry that does not contain metal ions are used to chemical mechanically polish and to planarize the dielectric layer. The fixed base includes a base and evenly distributed polishing abrasives fixed onto the base.