Abstract: Techniques to reduce signal interference between wired signals communicated within an electronic device and wireless signals transmitted to or received from antennas of the electronic device are disclosed. The electronic device includes an interposer with an inner fence and an outer fence having offset gaps to prevent a pathway otherwise formed by overlapping tabs, where the pathway allows noise leakage from the wired signals. In some embodiments, the electronic device (e.g., in a main logic board package) includes a ground fencing of ground vias to prevent the noise leakage from harmonics associated with signal vias communicating the wired signals. The spacing between the ground vias is based on frequencies of signals that the ground vias are intended to block.

Abstract: Devices are disclosed that include a wideband millimeter wave (mmW) via transition design for multilayer printed circuit boards (MLBs). In various instances embodiments, a via is dimensioned to provide impedance matching to stripline tracing connected at the end of the via. Impedance matching in the via may eliminate the need for an impedance matching section on the stripline tracing. In some instances, the dimensions of the via pad diameter and the via keepout diameter are selected to tune a via transition structure to selected frequencies and/or frequency bandwidths.

Abstract: Frequency-filtering circuitry is disclosed that rejects power of a wireless signal having an undesired frequency while causing a decreased power loss to a wireless signal having a desired frequency using distributed elements, rather than lumped elements. The frequency-filtering circuitry may reject at least 5 decibels of power of a wireless signal having a frequency over 32 gigahertz, while causing a power loss of at most 1.1 decibels to a wireless signal having a frequency lower than 29.5 gigahertz. The frequency-filtering circuitry may include a main branch, a first parallel branch coupled and parallel to the main branch via a first connecting trace, and a second parallel branch coupled and parallel to the main branch via a second connecting trace. The first connecting trace intersects the main branch and the first parallel branch, and the second connecting trace intersects the main branch and the second parallel branch.