Patents by Inventor Chi-Wang Chai

Chi-Wang Chai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210337192
    Abstract: An image processing method includes: determining a first block and a second block corresponding to a current block; dividing each of the current block, the first block and the second block into a plurality of clusters; for a cluster having a corresponding location within each of the current block, the first block and the second block, performing gradient calculations on pixel values within the cluster of the first block and pixel values within the cluster of the second block, and accordingly determining an adjustment value, wherein a window size of the cluster used in the gradient calculations is one or zero; and for a pixel within the cluster of the current block, referring to a pixel value of the pixel of the first block, a pixel value of the pixel of the second block and the adjustment value to calculate a pixel value of the pixel of the current block.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Inventors: Weimin Zeng, Chi-Wang Chai, Wujun Chen, Jing Wang, Rong Zhang
  • Publication number: 20210306677
    Abstract: A bit rate control method includes the following operations: receiving a first target bit of a video to be coded; determining a second target bit for first coding tree units (CTUs) in CTUs of the video according to the first target bit; determining a fourth target bit of at least one fourth CTU in the CTUs according to an actual bit of at least one second CTU in the CTUs and a third target bit of at least one third CTU in the CTUs, in which the at least one second CTU is completely coded, the at least one third CTU is completely coded, and a coding of the at least one fourth CTU is not started; and sequentially adjusting at least one coding parameter for coding the video according to the second target bit, the third target bit, and the fourth target bit.
    Type: Application
    Filed: January 5, 2021
    Publication date: September 30, 2021
    Inventors: WEI-MIN ZENG, CHI-WANG CHAI, QING-XI HE, XIAO-HUA XI, RONG ZHANG
  • Patent number: 11051013
    Abstract: A selection module for selecting an intra mode comprises a histogram of oriented gradient (HOG) module, for receiving a coding unit (CU), to select four angular modes from 33 angular modes of the CU, a DC mode of the CU and a planar mode of the CU; and a decision module, couple to the HOG module, for receiving the six modes from the HOG module, to compare the six modes according to a Split Sum of Absolute Transformed Difference (SSATD) algorithm, to select one of the six modes.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: June 29, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chi-Wang Chai, Weimin Zeng, Wujun Chen, Jing Wang, Wei Pu
  • Publication number: 20210144368
    Abstract: A selection module for selecting an intra mode comprises a histogram of oriented gradient (HOG) module, for receiving a coding unit (CU), to select four angular modes from 33 angular modes of the CU, a DC mode of the CU and a planar mode of the CU; and a decision module, couple to the HOG module, for receiving the six modes from the HOG module, to compare the six modes according to a Split Sum of Absolute Transformed Difference (SSATD) algorithm, to select one of the six modes.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 13, 2021
    Inventors: Chi-Wang Chai, Weimin Zeng, Wujun Chen, Jing Wang, Wei Pu
  • Patent number: 10972767
    Abstract: A transmitter for handling multiple formats of a video sequence, comprises a preprocessing module, for receiving a first format of a video sequence, to generate metadata of a second format of the video sequence according to the first format of the video sequence and the second format of the video sequence; and an encoder, couple to the preprocessing module, for transmitting the first format of the video sequence and the metadata in a bit stream to a receiver.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: April 6, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Lingzhi Liu, Li Liu, Jing Wang, Wujun Chen, Qingxi He, Wei Pu, Weimin Zeng, Chi-Wang Chai
  • Publication number: 20190132617
    Abstract: A transmitter for handling multiple formats of a video sequence, comprises a preprocessing module, for receiving a first format of a video sequence, to generate metadata of a second format of the video sequence according to the first format of the video sequence and the second format of the video sequence; and an encoder, couple to the preprocessing module, for transmitting the first format of the video sequence and the metadata in a bit stream to a receiver.
    Type: Application
    Filed: October 29, 2018
    Publication date: May 2, 2019
    Inventors: Lingzhi Liu, Li Liu, Jing Wang, Wujun Chen, Qingxi He, Wei Pu, Weimin Zeng, Chi-Wang Chai
  • Patent number: 7557740
    Abstract: A decoding method is adapted to be implemented using a Context-based Adaptive Binary Arithmetic Coding (CABAC) decoding apparatus, and includes: initializing a plurality of context variables; storing the context variables; performing arithmetic decoding of a syntax element according to the context variables so as to output a decoded syntax element and an update signal; and updating at least one of the context variables according to the update signal. At least one of the context variables is pre-initialized in the initializing step before a bit stream ready.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: July 7, 2009
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chao-An Hsieh, Chi-Wang Chai, Kai Wen Chuang
  • Publication number: 20090154568
    Abstract: A multimedia decoding apparatus and method thereof can accelerate decoding speed. The multimedia decoding apparatus is adapted for decoding a multimedia packet that includes a header portion and a data portion. The multimedia decoding apparatus includes a header parsing module, a storage unit, and a data processing module. The header parsing module receives the multimedia packet and parses the header portion of the multimedia packet to output at least one parameter. The storage unit is coupled to the header parsing module for storing the parameter and the data portion of the multimedia packet. The data processing module is coupled to the storage unit for processing the data portion of the multimedia packet according to the parameter. When the data processing module processes the data portion of the multimedia packet, the header parsing module parses the header portion of another multimedia packet simultaneously.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 18, 2009
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yu-Ting Chuang, Chi-Wang Chai
  • Patent number: 5870497
    Abstract: A decoder for compressed video signals comprises a central processing unit (CPU), a dynamic random access memory (DRAM) controller, a variable length code (VLC) decoder, a pixel filter and a video output unit. The microcoded CPU performs dequantization and inverse cosine transform using a pipelined data path, which includes both general purpose and special purpose hardware. In one embodiment, the VLC decoder is implemented as a table-driven state machine where the table contains both control information and decoded values.
    Type: Grant
    Filed: May 28, 1992
    Date of Patent: February 9, 1999
    Assignee: C-Cube Microsystems
    Inventors: David E. Galbi, Stephen C. Purcell, Eric Chi-Wang Chai