Patents by Inventor Chi-Wang Chai

Chi-Wang Chai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12267489
    Abstract: A coding algorithm encodes consecutive frames of a video sequence and realizes distributed Gradual Decoding Refresh. The consecutive frames include a first frame, a second frame, and a third frame, and each frame is composed of (X+Y+Z) columns of coding tree units. The algorithm includes: coding X columns of the first frame in an intra coding manner and coding the other columns of the first frame in an inter coding manner and/or the intra coding manner; coding X columns of the second frame in the inter coding manner, coding Y columns of the second frame in the intra coding manner, and coding Z columns of the second frame in the inter and/or intra coding manner(s); and coding X and Y columns of the third frame in the inter coding manner, and coding Z columns of the third frame in the intra coding manner. The X/Y/Z columns (intra-coded columns) are inconsecutive.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: April 1, 2025
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Wei-Min Zeng, Chi-Wang Chai, Wu-Jun Chen, Wei Li, Rong Zhang
  • Patent number: 12262057
    Abstract: A method for compressing images based on joint photographic experts group (JPEG) standard includes: compressing data of one or more first image blocks with a first compression level to produce compression data of the one or more first image blocks; adjusting the first compression level to obtain a second compression level according to at least one of a data size-related index regarding the compression data of the one or more first image blocks or a transmission-related index regarding transmission of the compression data of the one or more first image blocks; and compressing data of a second image block with the second compression level.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: March 25, 2025
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hsu-Jung Tung, Chi-Wang Chai, Weimin Zeng, Yi-Chen Tseng
  • Patent number: 12212761
    Abstract: The present invention provides an encoder including a quantization circuit, a control circuit and an encoding circuit is disclosed. The quantization circuit is configured to generate quantized data corresponding to a CTU according to image data, wherein the CTU comprises at least one TU. The control circuit is configured to determine a number of allocated bits for each TU in the CTU, where the number of allocated bits for each TU is determined based on a sum of remaining bits of the TUs that have been encoded. The encoding circuit is configured to encode each TU to obtain encoded data according to the number of allocated bits of the TU in the CTU.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: January 28, 2025
    Assignee: Realtek Semiconductor Corp.
    Inventors: Weimin Zeng, Chi-Wang Chai, Wei Pu, Wujun Chen, Wei Li
  • Patent number: 12120311
    Abstract: The present invention provides an encoder including a quantization circuit, an encoding circuit, an energy parameter calculation circuit and a quantization parameter determination circuit. The quantization circuit is configured to perform quantization operations on a plurality of CTUs in image data in sequence to generate quantized data respectively corresponding to the plurality of CTUs. The encoding circuit is configured to perform encoding operations on the quantized data of the plurality of CTUs in sequence to generate encoded data. The energy parameter calculation circuit is configured to receive the image data, and calculate a plurality of energy parameters respectively corresponding to the plurality of CTUs in the image data. The quantization parameter determination circuit is configured to determine a plurality of quantization parameters of the plurality of CTUs according to at least a portion of the plurality of energy parameters, for the quantization circuit to perform the quantization operations.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: October 15, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, Wujun Chen, Wei Pu
  • Patent number: 12120327
    Abstract: The present invention provides a receiver including a decoder, an upscale circuit and a color space conversion circuit. The decoder is configured to decode a video stream to generate a base layer and an enhancement layer. The upscale circuit is configured to perform an upscaling operation on the base layer to generate an upscaled base layer, wherein the upscaled base layer comprises luminance values of a plurality of pixels of a frame, and the enhancement layer comprises residuals of the plurality of pixels of the frame. The color space conversion circuit is configured to use a conversion matrix to combine the upscaled base layer and the enhancement layer to generate output video data.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: October 15, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chi-Wang Chai
  • Publication number: 20240267541
    Abstract: The present invention provides an encoder including a quantization circuit, a control circuit and an encoding circuit is disclosed. The quantization circuit is configured to generate quantized data corresponding to a CTU according to image data, wherein the CTU comprises at least one TU. The control circuit is configured to determine a number of allocated bits for each TU in the CTU, where the number of allocated bits for each TU is determined based on a sum of remaining bits of the TUs that have been encoded. The encoding circuit is configured to encode each TU to obtain encoded data according to the number of allocated bits of the TU in the CTU.
    Type: Application
    Filed: February 8, 2023
    Publication date: August 8, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Weimin Zeng, Chi-Wang Chai, Wei Pu, Wujun Chen, Wei Li
  • Publication number: 20240267528
    Abstract: The present invention provides an encoder including a quantization circuit, an encoding circuit, an energy parameter calculation circuit and a quantization parameter determination circuit. The quantization circuit is configured to perform quantization operations on a plurality of CTUs in image data in sequence to generate quantized data respectively corresponding to the plurality of CTUs. The encoding circuit is configured to perform encoding operations on the quantized data of the plurality of CTUs in sequence to generate encoded data. The energy parameter calculation circuit is configured to receive the image data, and calculate a plurality of energy parameters respectively corresponding to the plurality of CTUs in the image data. The quantization parameter determination circuit is configured to determine a plurality of quantization parameters of the plurality of CTUs according to at least a portion of the plurality of energy parameters, for the quantization circuit to perform the quantization operations.
    Type: Application
    Filed: February 8, 2023
    Publication date: August 8, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, Wujun Chen, Wei Pu
  • Publication number: 20240259577
    Abstract: The present invention provides a receiver including a decoder, an upscale circuit and a color space conversion circuit. The decoder is configured to decode a video stream to generate a base layer and an enhancement layer. The upscale circuit is configured to perform an upscaling operation on the base layer to generate an upscaled base layer, wherein the upscaled base layer comprises luminance values of a plurality of pixels of a frame, and the enhancement layer comprises residuals of the plurality of pixels of the frame. The color space conversion circuit is configured to use a conversion matrix to combine the upscaled base layer and the enhancement layer to generate output video data.
    Type: Application
    Filed: February 1, 2023
    Publication date: August 1, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventor: Chi-Wang Chai
  • Publication number: 20240187572
    Abstract: A coding algorithm encodes consecutive frames of a video sequence and realizes distributed Gradual Decoding Refresh. The consecutive frames include a first frame, a second frame, and a third frame, and each frame is composed of (X+Y+Z) columns of coding tree units. The algorithm includes: coding X columns of the first frame in an intra coding manner and coding the other columns of the first frame in an inter coding manner and/or the intra coding manner; coding X columns of the second frame in the inter coding manner, coding Y columns of the second frame in the intra coding manner, and coding Z columns of the second frame in the inter and/or intra coding manner(s); and coding X and Y columns of the third frame in the inter coding manner, and coding Z columns of the third frame in the intra coding manner. The X/Y/Z columns (intra-coded columns) are inconsecutive.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 6, 2024
    Inventors: WEI-MIN ZENG, CHI-WANG CHAI, WU-JUN CHEN, WEI LI, RONG ZHANG
  • Publication number: 20230396811
    Abstract: A method and an electronic device for processing video coding are provided. The electronic device for processing video coding includes a storage unit, a coding tree generation module, and a decision tree module. The storage unit stores an input video. The input video includes a plurality of frames. The electronic device for processing video performs following steps of: acquiring a target block in each of the frames, where the target block has at least one coding unit; loading the target block to the coding tree generation module to output a first coding tree and a second coding tree; generating an output decision tree according to the first coding tree and the second coding tree; and outputting streaming data according to the output decision tree and the frames.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Wei-Min Zeng, Chi-Wang Chai, Wei Li, Jing Wang, Wu-Jun Chen
  • Publication number: 20230308687
    Abstract: A method for compressing images based on joint photographic experts group (JPEG) standard includes: compressing data of one or more first image blocks with a first compression level to produce compression data of the one or more first image blocks; adjusting the first compression level to obtain a second compression level according to at least one of a data size-related index regarding the compression data of the one or more first image blocks or a transmission-related index regarding transmission of the compression data of the one or more first image blocks; and compressing data of a second image block with the second compression level.
    Type: Application
    Filed: March 22, 2022
    Publication date: September 28, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: Hsu-Jung Tung, Chi-Wang Chai, Weimin Zeng, Yi-Chen Tseng
  • Patent number: 11770524
    Abstract: A loop filter utilized in an encoder includes a constrained directional enhancement filter and a decision circuit. The constrained directional enhancement filter is arranged to process multiple frames, wherein for a first frame in the multiple frames, the constrained directional enhancement filter determines a best filter strength of each block in the first frame in a first filter strength list, and determines a second filter strength list according to content of the first frame. The decision circuit is coupled to the constrained directional enhancement filter, and is arranged to record which index in the first filter strength list is the best filter strength corresponding to each block in the first frame, and provide the first filter strength list and the index corresponding to each block to an encoding circuit of the encoder as an output of the encoder.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: September 26, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, Rong Zhang, Wujun Chen
  • Patent number: 11750800
    Abstract: A prediction circuit in an encoder utilizes a specific partition mode to process a super block for generating a plurality of reconstructed pixel values for each block in the super block, and the reconstructed pixel values of each block are directly utilized as reference pixels for other blocks to perform intra-frame prediction, so as to improve the efficiency of the encoder.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: September 5, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Weimin Zeng, Chi-Wang Chai, Wei Pu, Wujun Chen, Jing Wang, Wei Li
  • Publication number: 20230141735
    Abstract: A loop filter utilized in an encoder includes a constrained directional enhancement filter and a decision circuit. The constrained directional enhancement filter is arranged to process multiple frames, wherein for a first frame in the multiple frames, the constrained directional enhancement filter determines a best filter strength of each block in the first frame in a first filter strength list, and determines a second filter strength list according to content of the first frame. The decision circuit is coupled to the constrained directional enhancement filter, and is arranged to record which index in the first filter strength list is the best filter strength corresponding to each block in the first frame, and provide the first filter strength list and the index corresponding to each block to an encoding circuit of the encoder as an output of the encoder.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 11, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, Rong Zhang, Wujun Chen
  • Patent number: 11523117
    Abstract: An encoder includes a frame level processing circuit, a coding tree unit (CTU) level processing circuit and an encoding circuit. The frame level processing circuit is arranged to calculate a bit number of a current frame according a target bitrate and a frame rate, and the frame level processing circuit is further arranged to calculate a quantization parameter of the current frame according to the bit number of the current frame and at least one parameter. The CTU level processing circuit is arranged to use an adaptive quantization mode to adjust the quantization parameter to generate an adjusted quantization parameter. The encoding circuit is arranged to encode the current frame to generate output data according to the adjusted quantization parameter.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: December 6, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, QingXi He, Wujun Chen, Rong Zhang
  • Publication number: 20220303538
    Abstract: An encoder includes a frame level processing circuit, a coding tree unit (CTU) level processing circuit and an encoding circuit. The frame level processing circuit is arranged to calculate a bit number of a current frame according a target bitrate and a frame rate, and the frame level processing circuit is further arranged to calculate a quantization parameter of the current frame according to the bit number of the current frame and at least one parameter. The CTU level processing circuit is arranged to use an adaptive quantization mode to adjust the quantization parameter to generate an adjusted quantization parameter. The encoding circuit is arranged to encode the current frame to generate output data according to the adjusted quantization parameter.
    Type: Application
    Filed: March 22, 2021
    Publication date: September 22, 2022
    Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, QingXi He, Wujun Chen, Rong Zhang
  • Patent number: 11272222
    Abstract: A bit rate control method includes the following operations: receiving a first target bit of a video to be coded; determining a second target bit for first coding tree units (CTUs) in CTUs of the video according to the first target bit; determining a fourth target bit of at least one fourth CTU in the CTUs according to an actual bit of at least one second CTU in the CTUs and a third target bit of at least one third CTU in the CTUs, in which the at least one second CTU is completely coded, the at least one third CTU is not completely coded, and a coding of the at least one fourth CTU is not started; and sequentially adjusting at least one coding parameter for coding the video according to the second target bit, the third target bit, and the fourth target bit.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 8, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Wei-Min Zeng, Chi-Wang Chai, Qing-Xi He, Xiao-Hua Xi, Rong Zhang
  • Patent number: 11245896
    Abstract: Disclosed is a deblocking filter level decision method applicable to an image encoder and used for determining deblocking filter levels of N image frames. The method includes: determining whether a current quantization parameter of a current frame of the N image frames is the same as a previous quantization parameter of any previous frame of the N image frames; if the current quantization parameter is different from the previous quantization parameter, looking up M current deblocking filter reference levels in an established table according to the current quantization parameter and then determining M current deblocking filter levels of the current frame according to the M current deblocking filter reference levels, respectively; and if the current quantization parameter is the same as the previous quantization parameter, determining the M current deblocking filter levels of the current frame according to M previous deblocking filter levels of the previous frame, respectively.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 8, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Wei-Min Zeng, Chi-Wang Chai, Wei Li, Rong Zhang, Wu-Jun Chen
  • Publication number: 20210337192
    Abstract: An image processing method includes: determining a first block and a second block corresponding to a current block; dividing each of the current block, the first block and the second block into a plurality of clusters; for a cluster having a corresponding location within each of the current block, the first block and the second block, performing gradient calculations on pixel values within the cluster of the first block and pixel values within the cluster of the second block, and accordingly determining an adjustment value, wherein a window size of the cluster used in the gradient calculations is one or zero; and for a pixel within the cluster of the current block, referring to a pixel value of the pixel of the first block, a pixel value of the pixel of the second block and the adjustment value to calculate a pixel value of the pixel of the current block.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Inventors: Weimin Zeng, Chi-Wang Chai, Wujun Chen, Jing Wang, Rong Zhang
  • Publication number: 20210306677
    Abstract: A bit rate control method includes the following operations: receiving a first target bit of a video to be coded; determining a second target bit for first coding tree units (CTUs) in CTUs of the video according to the first target bit; determining a fourth target bit of at least one fourth CTU in the CTUs according to an actual bit of at least one second CTU in the CTUs and a third target bit of at least one third CTU in the CTUs, in which the at least one second CTU is completely coded, the at least one third CTU is completely coded, and a coding of the at least one fourth CTU is not started; and sequentially adjusting at least one coding parameter for coding the video according to the second target bit, the third target bit, and the fourth target bit.
    Type: Application
    Filed: January 5, 2021
    Publication date: September 30, 2021
    Inventors: WEI-MIN ZENG, CHI-WANG CHAI, QING-XI HE, XIAO-HUA XI, RONG ZHANG