Patents by Inventor Chi-Wang Chai
Chi-Wang Chai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230396811Abstract: A method and an electronic device for processing video coding are provided. The electronic device for processing video coding includes a storage unit, a coding tree generation module, and a decision tree module. The storage unit stores an input video. The input video includes a plurality of frames. The electronic device for processing video performs following steps of: acquiring a target block in each of the frames, where the target block has at least one coding unit; loading the target block to the coding tree generation module to output a first coding tree and a second coding tree; generating an output decision tree according to the first coding tree and the second coding tree; and outputting streaming data according to the output decision tree and the frames.Type: ApplicationFiled: June 1, 2022Publication date: December 7, 2023Applicant: REALTEK SEMICONDUCTOR CORP.Inventors: Wei-Min Zeng, Chi-Wang Chai, Wei Li, Jing Wang, Wu-Jun Chen
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Publication number: 20230308687Abstract: A method for compressing images based on joint photographic experts group (JPEG) standard includes: compressing data of one or more first image blocks with a first compression level to produce compression data of the one or more first image blocks; adjusting the first compression level to obtain a second compression level according to at least one of a data size-related index regarding the compression data of the one or more first image blocks or a transmission-related index regarding transmission of the compression data of the one or more first image blocks; and compressing data of a second image block with the second compression level.Type: ApplicationFiled: March 22, 2022Publication date: September 28, 2023Applicant: Realtek Semiconductor Corp.Inventors: Hsu-Jung Tung, Chi-Wang Chai, Weimin Zeng, Yi-Chen Tseng
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Patent number: 11770524Abstract: A loop filter utilized in an encoder includes a constrained directional enhancement filter and a decision circuit. The constrained directional enhancement filter is arranged to process multiple frames, wherein for a first frame in the multiple frames, the constrained directional enhancement filter determines a best filter strength of each block in the first frame in a first filter strength list, and determines a second filter strength list according to content of the first frame. The decision circuit is coupled to the constrained directional enhancement filter, and is arranged to record which index in the first filter strength list is the best filter strength corresponding to each block in the first frame, and provide the first filter strength list and the index corresponding to each block to an encoding circuit of the encoder as an output of the encoder.Type: GrantFiled: November 11, 2021Date of Patent: September 26, 2023Assignee: Realtek Semiconductor Corp.Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, Rong Zhang, Wujun Chen
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Patent number: 11750800Abstract: A prediction circuit in an encoder utilizes a specific partition mode to process a super block for generating a plurality of reconstructed pixel values for each block in the super block, and the reconstructed pixel values of each block are directly utilized as reference pixels for other blocks to perform intra-frame prediction, so as to improve the efficiency of the encoder.Type: GrantFiled: May 30, 2022Date of Patent: September 5, 2023Assignee: Realtek Semiconductor Corp.Inventors: Weimin Zeng, Chi-Wang Chai, Wei Pu, Wujun Chen, Jing Wang, Wei Li
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Publication number: 20230141735Abstract: A loop filter utilized in an encoder includes a constrained directional enhancement filter and a decision circuit. The constrained directional enhancement filter is arranged to process multiple frames, wherein for a first frame in the multiple frames, the constrained directional enhancement filter determines a best filter strength of each block in the first frame in a first filter strength list, and determines a second filter strength list according to content of the first frame. The decision circuit is coupled to the constrained directional enhancement filter, and is arranged to record which index in the first filter strength list is the best filter strength corresponding to each block in the first frame, and provide the first filter strength list and the index corresponding to each block to an encoding circuit of the encoder as an output of the encoder.Type: ApplicationFiled: November 11, 2021Publication date: May 11, 2023Applicant: Realtek Semiconductor Corp.Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, Rong Zhang, Wujun Chen
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Patent number: 11523117Abstract: An encoder includes a frame level processing circuit, a coding tree unit (CTU) level processing circuit and an encoding circuit. The frame level processing circuit is arranged to calculate a bit number of a current frame according a target bitrate and a frame rate, and the frame level processing circuit is further arranged to calculate a quantization parameter of the current frame according to the bit number of the current frame and at least one parameter. The CTU level processing circuit is arranged to use an adaptive quantization mode to adjust the quantization parameter to generate an adjusted quantization parameter. The encoding circuit is arranged to encode the current frame to generate output data according to the adjusted quantization parameter.Type: GrantFiled: March 22, 2021Date of Patent: December 6, 2022Assignee: Realtek Semiconductor Corp.Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, QingXi He, Wujun Chen, Rong Zhang
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Publication number: 20220303538Abstract: An encoder includes a frame level processing circuit, a coding tree unit (CTU) level processing circuit and an encoding circuit. The frame level processing circuit is arranged to calculate a bit number of a current frame according a target bitrate and a frame rate, and the frame level processing circuit is further arranged to calculate a quantization parameter of the current frame according to the bit number of the current frame and at least one parameter. The CTU level processing circuit is arranged to use an adaptive quantization mode to adjust the quantization parameter to generate an adjusted quantization parameter. The encoding circuit is arranged to encode the current frame to generate output data according to the adjusted quantization parameter.Type: ApplicationFiled: March 22, 2021Publication date: September 22, 2022Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, QingXi He, Wujun Chen, Rong Zhang
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Patent number: 11272222Abstract: A bit rate control method includes the following operations: receiving a first target bit of a video to be coded; determining a second target bit for first coding tree units (CTUs) in CTUs of the video according to the first target bit; determining a fourth target bit of at least one fourth CTU in the CTUs according to an actual bit of at least one second CTU in the CTUs and a third target bit of at least one third CTU in the CTUs, in which the at least one second CTU is completely coded, the at least one third CTU is not completely coded, and a coding of the at least one fourth CTU is not started; and sequentially adjusting at least one coding parameter for coding the video according to the second target bit, the third target bit, and the fourth target bit.Type: GrantFiled: January 5, 2021Date of Patent: March 8, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Wei-Min Zeng, Chi-Wang Chai, Qing-Xi He, Xiao-Hua Xi, Rong Zhang
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Patent number: 11245896Abstract: Disclosed is a deblocking filter level decision method applicable to an image encoder and used for determining deblocking filter levels of N image frames. The method includes: determining whether a current quantization parameter of a current frame of the N image frames is the same as a previous quantization parameter of any previous frame of the N image frames; if the current quantization parameter is different from the previous quantization parameter, looking up M current deblocking filter reference levels in an established table according to the current quantization parameter and then determining M current deblocking filter levels of the current frame according to the M current deblocking filter reference levels, respectively; and if the current quantization parameter is the same as the previous quantization parameter, determining the M current deblocking filter levels of the current frame according to M previous deblocking filter levels of the previous frame, respectively.Type: GrantFiled: February 26, 2021Date of Patent: February 8, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Wei-Min Zeng, Chi-Wang Chai, Wei Li, Rong Zhang, Wu-Jun Chen
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Publication number: 20210337192Abstract: An image processing method includes: determining a first block and a second block corresponding to a current block; dividing each of the current block, the first block and the second block into a plurality of clusters; for a cluster having a corresponding location within each of the current block, the first block and the second block, performing gradient calculations on pixel values within the cluster of the first block and pixel values within the cluster of the second block, and accordingly determining an adjustment value, wherein a window size of the cluster used in the gradient calculations is one or zero; and for a pixel within the cluster of the current block, referring to a pixel value of the pixel of the first block, a pixel value of the pixel of the second block and the adjustment value to calculate a pixel value of the pixel of the current block.Type: ApplicationFiled: April 24, 2020Publication date: October 28, 2021Inventors: Weimin Zeng, Chi-Wang Chai, Wujun Chen, Jing Wang, Rong Zhang
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Publication number: 20210306677Abstract: A bit rate control method includes the following operations: receiving a first target bit of a video to be coded; determining a second target bit for first coding tree units (CTUs) in CTUs of the video according to the first target bit; determining a fourth target bit of at least one fourth CTU in the CTUs according to an actual bit of at least one second CTU in the CTUs and a third target bit of at least one third CTU in the CTUs, in which the at least one second CTU is completely coded, the at least one third CTU is completely coded, and a coding of the at least one fourth CTU is not started; and sequentially adjusting at least one coding parameter for coding the video according to the second target bit, the third target bit, and the fourth target bit.Type: ApplicationFiled: January 5, 2021Publication date: September 30, 2021Inventors: WEI-MIN ZENG, CHI-WANG CHAI, QING-XI HE, XIAO-HUA XI, RONG ZHANG
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Patent number: 11051013Abstract: A selection module for selecting an intra mode comprises a histogram of oriented gradient (HOG) module, for receiving a coding unit (CU), to select four angular modes from 33 angular modes of the CU, a DC mode of the CU and a planar mode of the CU; and a decision module, couple to the HOG module, for receiving the six modes from the HOG module, to compare the six modes according to a Split Sum of Absolute Transformed Difference (SSATD) algorithm, to select one of the six modes.Type: GrantFiled: November 12, 2019Date of Patent: June 29, 2021Assignee: Realtek Semiconductor Corp.Inventors: Chi-Wang Chai, Weimin Zeng, Wujun Chen, Jing Wang, Wei Pu
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Publication number: 20210144368Abstract: A selection module for selecting an intra mode comprises a histogram of oriented gradient (HOG) module, for receiving a coding unit (CU), to select four angular modes from 33 angular modes of the CU, a DC mode of the CU and a planar mode of the CU; and a decision module, couple to the HOG module, for receiving the six modes from the HOG module, to compare the six modes according to a Split Sum of Absolute Transformed Difference (SSATD) algorithm, to select one of the six modes.Type: ApplicationFiled: November 12, 2019Publication date: May 13, 2021Inventors: Chi-Wang Chai, Weimin Zeng, Wujun Chen, Jing Wang, Wei Pu
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Patent number: 10972767Abstract: A transmitter for handling multiple formats of a video sequence, comprises a preprocessing module, for receiving a first format of a video sequence, to generate metadata of a second format of the video sequence according to the first format of the video sequence and the second format of the video sequence; and an encoder, couple to the preprocessing module, for transmitting the first format of the video sequence and the metadata in a bit stream to a receiver.Type: GrantFiled: October 29, 2018Date of Patent: April 6, 2021Assignee: Realtek Semiconductor Corp.Inventors: Lingzhi Liu, Li Liu, Jing Wang, Wujun Chen, Qingxi He, Wei Pu, Weimin Zeng, Chi-Wang Chai
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Publication number: 20190132617Abstract: A transmitter for handling multiple formats of a video sequence, comprises a preprocessing module, for receiving a first format of a video sequence, to generate metadata of a second format of the video sequence according to the first format of the video sequence and the second format of the video sequence; and an encoder, couple to the preprocessing module, for transmitting the first format of the video sequence and the metadata in a bit stream to a receiver.Type: ApplicationFiled: October 29, 2018Publication date: May 2, 2019Inventors: Lingzhi Liu, Li Liu, Jing Wang, Wujun Chen, Qingxi He, Wei Pu, Weimin Zeng, Chi-Wang Chai
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Patent number: 7557740Abstract: A decoding method is adapted to be implemented using a Context-based Adaptive Binary Arithmetic Coding (CABAC) decoding apparatus, and includes: initializing a plurality of context variables; storing the context variables; performing arithmetic decoding of a syntax element according to the context variables so as to output a decoded syntax element and an update signal; and updating at least one of the context variables according to the update signal. At least one of the context variables is pre-initialized in the initializing step before a bit stream ready.Type: GrantFiled: April 18, 2008Date of Patent: July 7, 2009Assignee: Realtek Semiconductor Corp.Inventors: Chao-An Hsieh, Chi-Wang Chai, Kai Wen Chuang
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Publication number: 20090154568Abstract: A multimedia decoding apparatus and method thereof can accelerate decoding speed. The multimedia decoding apparatus is adapted for decoding a multimedia packet that includes a header portion and a data portion. The multimedia decoding apparatus includes a header parsing module, a storage unit, and a data processing module. The header parsing module receives the multimedia packet and parses the header portion of the multimedia packet to output at least one parameter. The storage unit is coupled to the header parsing module for storing the parameter and the data portion of the multimedia packet. The data processing module is coupled to the storage unit for processing the data portion of the multimedia packet according to the parameter. When the data processing module processes the data portion of the multimedia packet, the header parsing module parses the header portion of another multimedia packet simultaneously.Type: ApplicationFiled: December 12, 2007Publication date: June 18, 2009Applicant: REALTEK SEMICONDUCTOR CORP.Inventors: Yu-Ting Chuang, Chi-Wang Chai
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Patent number: 5870497Abstract: A decoder for compressed video signals comprises a central processing unit (CPU), a dynamic random access memory (DRAM) controller, a variable length code (VLC) decoder, a pixel filter and a video output unit. The microcoded CPU performs dequantization and inverse cosine transform using a pipelined data path, which includes both general purpose and special purpose hardware. In one embodiment, the VLC decoder is implemented as a table-driven state machine where the table contains both control information and decoded values.Type: GrantFiled: May 28, 1992Date of Patent: February 9, 1999Assignee: C-Cube MicrosystemsInventors: David E. Galbi, Stephen C. Purcell, Eric Chi-Wang Chai