Abstract: An apparatus and method for efficiently generating clock signals. An integrated circuit includes multiple clock dividers both at its I/O boundaries and across its semiconductor die. A clock divider receives an input clock signal, and an indication of a reduction factor that is a positive, non-zero and a non-integer value less than one. The clock divider generates an output clock signal based on the input clock signal and the reduction factor. The reduction factor can be an M-bit pattern where M is a positive, non-zero integer greater than one. Therefore, the clock divider generates the output clock signal with a reduced clock rate that has a smallest configurable granularity that is 1/M of the input clock frequency. An asserted bit in the M-bit pattern indicates that the output clock signal should have an asserted value during a corresponding clock cycle of the input clock signal.

Abstract: An apparatus and method for efficiently generating clock signals. An integrated circuit includes multiple clock dividers both at its I/O boundaries and across its semiconductor die. A clock divider receives an input clock signal, and an indication of a reduction factor that is a positive, non-zero and a non-integer value less than one. The clock divider generates an output clock signal based on the input clock signal and the reduction factor. The reduction factor can be an M-bit pattern where M is a positive, non-zero integer greater than one. Therefore, the clock divider generates the output clock signal with a reduced clock rate that has a smallest configurable granularity that is 1/M of the input clock frequency. An asserted bit in the M-bit pattern indicates that the output clock signal should have an asserted value during a corresponding clock cycle of the input clock signal.

Abstract: An integrated circuit film for a smart card, such as a Micro SIM card or a Mini UICC card, is provided. The integrated circuit film includes a flexible print circuit board (FPC) and an integrated circuit chip, and the integrated circuit chip has an ATR (Answer to Reset) signal generating device. When a terminal issues a Reset signal, this Reset signal is sent to the smart card and the ATR signal generating device, respectively via circuits of the FPC, whereby the ATR signal generating device generates ATR signal and send back to the terminal.

Abstract: An integrated circuit film for a smart card, such as a Micro SIM card or a Mini UICC card, is provided. The integrated circuit film includes a flexible print circuit board (FPC) and an integrated circuit chip, and the integrated circuit chip has an ATR (Answer to Reset) signal generating device. When a terminal issues a Reset signal, this Reset signal is sent to the smart card and the ATR signal generating device, respectively via circuits of the FPC, whereby the ATR signal generating device generates ATR signal and send back to the terminal.

Abstract: A method and apparatus handling payment transactions in a system using mobile communication devices as stored value devices are disclosed. A transaction operations server receives multiple records of the transaction from the stored value device—one via a communication channel through the telecommunication provider network, and another via an independent communication channel. The records are reconciled at the transaction server for transaction verification.