Patents by Inventor Chi-Wei Chiang

Chi-Wei Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190295849
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Inventors: I-Fan Chang, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, Jie-Ning Yang, Chi-Ju Lee, Chun-Ting Chiang, Bo-Yu Su, Chih-Wei Lin, Dien-Yang Lu
  • Patent number: 10422744
    Abstract: Provided is an interferometer for inspecting a test sample. The interferometer includes: a light source for providing a light beam; a beam splitting element, splitting the light beam into first and second incident light, wherein the first incident light is reflected by the test sample into first reflection light; a reflecting element, reflecting the second incident light into second reflection light; an optical detection element, receiving the first and the second reflection light into an interference signal; and a signal processing module, coupled to the optical detection element, for performing spatial differential calculation on the interference signal to generate a demodulation image of the test sample.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: September 24, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ting-Wei Chang, Yuan-Chin Lee, Chi-Shen Chang, Hung-Chih Chiang, Shuen-Chen Chen
  • Patent number: 10388749
    Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: August 20, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang, Chun-Ting Chiang, Chih-Wei Lin, Bo-Yu Su, Chi-Ju Lee
  • Publication number: 20190238792
    Abstract: The present disclosure provides a conversion device, a connection conference system and a connection conference method. This method includes steps as follows. A computer device executes video telephony software. A conference host establishes audio and video communications with a user device through network. The conference connection host receives a first audio signal and a first video signal outputted from the user device. The first audio signal and the first video signal are converted into a first converted audio signal and a first converted video signal supported by the video telephony software, and then the first converted audio signal and the first converted video signal are transmitted to the computer device.
    Type: Application
    Filed: October 21, 2018
    Publication date: August 1, 2019
    Inventors: Ming-Kang CHUANG, Chi-Wei CHIANG
  • Patent number: 10366896
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: July 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Fan Chang, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, Jie-Ning Yang, Chi-Ju Lee, Chun-Ting Chiang, Bo-Yu Su, Chih-Wei Lin, Dien-Yang Lu
  • Publication number: 20190229715
    Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Inventors: Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh, Che Min Huang
  • Publication number: 20190147132
    Abstract: A semiconductor device including: standard functional cells located in a logic area; standard spare cells arranged in a spare region of the logic area; and a metallization layer including segments, some of the segments being included in corresponding ones of the functional cells, some of the segments being included in corresponding ones of the spare cells, and some of the segments representing strap lines; and wherein a first pitch of the standard spare cells is based on a second pitch of the strap lines.
    Type: Application
    Filed: November 12, 2018
    Publication date: May 16, 2019
    Inventors: Mao-Wei CHIU, Ting-Wei CHIANG, Hui-Zhong ZHUANG, Li-Chun TIEN, Chi-Yu LU
  • Publication number: 20190139895
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a trench. The trench has an inner wall and a bottom surface. The method includes forming a second mask layer in the trench. The method includes removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The second trench exposes the bottom surface and is over a first portion of the dielectric layer. The remaining second mask layer covers the inner wall. The method includes removing the first portion, the first mask layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.
    Type: Application
    Filed: January 31, 2018
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Cherng JENG, Shyh-Wei CHENG, Yun CHANG, Chen-Chieh CHIANG, Jung-Chi JENG
  • Publication number: 20180038816
    Abstract: The present invention provides a gas sensor structure comprising a gas sensing chip. The back of the sensing material is a hollow structure. An insulating layer is below the sensing material. A micro heating is disposed surrounding the sensing material. The sensing material adheres to sensing electrodes. The sensing material is a complex structure including a metal oxide semiconductor and a roughened lanthanum-carbonate gas sensing layer. The thickness of the metal oxide semiconductor is between 0.2 ?m and 10 ?m; the thickness of the roughened lanthanum-carbonate gas sensing layer is between 0.1 ?m and 4 ?m; and the size of the back etching holes is smaller than 1*1 mm. By using the gas sensor structure according to the present invention, a suspended gas sensing structure can be fabricated on a silicon substrate and the chip size can be minimized.
    Type: Application
    Filed: December 6, 2016
    Publication date: February 8, 2018
    Inventors: YU-JEN HSIAO, TING-JEN HSUEH, YU-TE LIN, YEN-HSI LI, JIA-MIN SHIEH, CHIEN-WEI LIU, CHI-WEI CHIANG
  • Patent number: 7568099
    Abstract: A method for avoiding IKE process conflict includes the steps in that a first gateway sends a first IKE request packet and receives a second IKE request packet from a second gateway. Afterward a decision is performed to decide whether the first gateway is an initiator or a responder. If the first gateway is an initiator, the first gateway will drop the received second IKE request packets and continue working as an initiator. If the first gateway is a responder, then first gateway will cancel the pre-sent first IKE request packet and work as a responder, and will perform IKE negotiation according to the second IKE packet. The present invention also discloses an apparatus for realizing above method.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: July 28, 2009
    Assignee: Zyxel Communications Corporation
    Inventors: Chia-Yuan Chen, Chi-Wei Chiang
  • Publication number: 20060215674
    Abstract: A method for avoiding IKE process conflict includes the steps in that a first gateway sends a first IKE request packet and receives a second IKE request packet from a second gateway. Afterward a decision is performed to decide whether the first gateway is an initiator or a responder. If the first gateway is an initiator, the first gateway will drop the received second IKE request packets and continue working as an initiator. If the first gateway is a responder, then first gateway will cancel the pre-sent first IKE request packet and work as a responder, and will perform IKE negotiation according to the second IKE packet. The present invention also discloses an apparatus for realizing above method.
    Type: Application
    Filed: March 25, 2005
    Publication date: September 28, 2006
    Inventors: Chia-Yuan Chen, Chi-Wei Chiang