Patents by Inventor Chi-Wei Chou
Chi-Wei Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240381724Abstract: A display may have a stretchable portion with hermetically sealed rigid pixel islands. A flexible interconnect region may be interposed between the hermetically sealed rigid pixel islands. The hermetically sealed rigid pixel islands may include organic light-emitting diode (OLED) pixels. A conductive cutting structure may have an undercut that causes a discontinuity in a conductive OLED layer to mitigate lateral leakage. The conductive cutting structure may also be electrically connected to a cathode for the OLED pixels and provide a cathode voltage to the cathode. First and second inorganic passivation layers may be formed over the OLED pixels. Multiple discrete portions of an organic inkjet printed layer may be interposed between the first and second inorganic passivation layers.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: Prashant Mandlik, Bhadrinarayana Lalgudi Visweswaran, Xuesong Lu, Weixin Li, Wenbing Hu, Yuchi Che, Tsung-Ting Tsai, Gihoon Choo, Shyuan Yang, Kuan-Yi Lee, An-Di Sheu, Chi-Wei Chou, Chin-Fu Lee, An-Hong Shen, Ko-Wei Chen, Kyounghwan Kim, Jae Won Choi, Warren S. Rieutort-Louis, Sungki Lee
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Publication number: 20240210995Abstract: A display may have a stretchable portion with hermetically sealed rigid pixel islands. A flexible interconnect region may be interposed between the hermetically sealed rigid pixel islands. The hermetically sealed rigid pixel islands may include organic light-emitting diode (OLED) pixels. A conductive cutting structure may have an undercut that causes a discontinuity in a conductive OLED layer to mitigate lateral leakage. The conductive cutting structure may also be electrically connected to a cathode for the OLED pixels and provide a cathode voltage to the cathode. First and second inorganic passivation layers may be formed over the OLED pixels. Multiple discrete portions of an organic inkjet printed layer may be interposed between the first and second inorganic passivation layers.Type: ApplicationFiled: October 10, 2023Publication date: June 27, 2024Inventors: Prashant Mandlik, Bhadrinarayana Lalgudi Visweswaran, Mahendra Chhabra, Chia-Hao Chang, Shiyi Liu, Siddharth Harikrishna Mohan, Zhen Zhang, Han-Chieh Chang, Yi Qiao, Yue Cui, Tyler R Kakuda, Michael Vosgueritchian, Sudirukkuge T. Jinasundera, Warren S Rieutort-Louis, Tsung-Ting Tsai, Jae Won Choi, Jiun-Jye Chang, Jean-Pierre S Guillou, Rui Liu, Po-Chun Yeh, Chieh Hung Yang, Ankit Mahajan, Takahide Ishii, Pei-Ling Lin, Pei Yin, Gwanwoo Park, Markus Einzinger, Martijn Kuik, Abhijeet S Bagal, Kyounghwan Kim, Jonathan H Beck, Chiang-Jen Hsiao, Chih-Hao Kung, Chih-Lei Chen, Chih-Yu Chung, Chuan-Jung Lin, Jung Yen Huang, Kuan-Chi Chen, Shinya Ono, Wei Jung Hsieh, Wei-Chieh Lin, Yi-Pu Chen, Yuan Ming Chiang, An-Di Sheu, Chi-Wei Chou, Chin-Fu Lee, Ko-Wei Chen, Kuan-Yi Lee, Weixin Li, Shin-Hung Yeh, Shyuan Yang, Themistoklis Afentakis, Asli Sirman, Baolin Tian, Han Liu
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Patent number: 9360895Abstract: An assembly for mounting a display device in a vehicle. The assembly includes a mounting plate having opposite edges, a front surface extending therebetween, and a rear surface opposite the front surface. The mounting plate is mountable to the vehicle with the front surface of the mounting plate facing outward. The assembly includes a first locking mechanism disposed proximate one edge of the mounting plate and a second locking mechanism disposed proximate the other edge. Each locking mechanism includes a jaw extending over the front surface of the mounting plate and pivotable between closed and open positions. Each jaw includes a resiliently deformable biasing member connected to the jaw and biasing the jaw towards the closed position. The assembly includes an electrical connector attached to the mounting plate. The electrical connector has an opening for mating with another connector.Type: GrantFiled: December 11, 2013Date of Patent: June 7, 2016Assignee: Panasonic Avionics CorporationInventors: Shrenik Shah, Chi-Wei Chou
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Patent number: 9263481Abstract: The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT.Type: GrantFiled: January 16, 2015Date of Patent: February 16, 2016Assignee: AU Optronics Corp.Inventors: Yi-Chen Chung, Chia-Yu Chen, Hui-Ling Ku, Yu-Hung Chen, Chi-Wei Chou, Fan-Wei Chang, Hsueh-Hsing Lu, Hung-Che Ting
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Patent number: 9147700Abstract: A manufacturing method of an array substrate includes following steps. A first photolithography process is performed to form a gate electrode on a substrate. A gate insulating layer is formed to cover the substrate and the gate electrode. A second photolithography process is performed to form a patterned semiconductor layer and a patterned etching stop layer. A semiconductor layer and an etching stop layer are successively formed on the gate insulating layer, and a second patterned photoresist is formed on the etching stop layer. The etching stop layer uncovered by the second patterned photoresist is removed. The semiconductor layer uncovered by the second patterned photoresist is removed for forming the patterned semiconductor on the gate insulating layer. A patterned etching stop layer is formed on the patterned semiconductor layer by etching the second patterned photoresist and the etching stop layer.Type: GrantFiled: January 15, 2015Date of Patent: September 29, 2015Assignee: AU Optronics Corp.Inventors: Yi-Chen Chung, Chia-Yu Chen, Hui-Ling Ku, Yu-Hung Chen, Chi-Wei Chou, Fan-Wei Chang, Hsueh-Hsing Lu, Hung-Che Ting
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Publication number: 20150123128Abstract: The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT.Type: ApplicationFiled: January 16, 2015Publication date: May 7, 2015Inventors: Yi-Chen Chung, Chia-Yu Chen, Hui-Ling Ku, Yu-Hung Chen, Chi-Wei Chou, Fan-Wei Chang, Hsueh-Hsing Lu, Hung-Che Ting
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Publication number: 20150126006Abstract: A manufacturing method of an array substrate includes following steps. A first photolithography process is performed to form a gate electrode on a substrate. A gate insulating layer is formed to cover the substrate and the gate electrode. A second photolithography process is performed to form a patterned semiconductor layer and a patterned etching stop layer. A semiconductor layer and an etching stop layer are successively formed on the gate insulating layer, and a second patterned photoresist is formed on the etching stop layer. The etching stop layer uncovered by the second patterned photoresist is removed. The semiconductor layer uncovered by the second patterned photoresist is removed for forming the patterned semiconductor on the gate insulating layer. A patterned etching stop layer is formed on the patterned semiconductor layer by etching the second patterned photoresist and the etching stop layer.Type: ApplicationFiled: January 15, 2015Publication date: May 7, 2015Inventors: Yi-Chen Chung, Chia-Yu Chen, Hui-Ling Ku, Yu-Hung Chen, Chi-Wei Chou, Fan-Wei Chang, Hsueh-Hsing Lu, Hung-Che Ting
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Patent number: 8969146Abstract: A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.Type: GrantFiled: September 14, 2012Date of Patent: March 3, 2015Assignee: AU Optronics Corp.Inventors: Yi-Chen Chung, Chia-Yu Chen, Hui-Ling Ku, Yu-Hung Chen, Chi-Wei Chou, Fan-Wei Chang, Hsueh-Hsing Lu, Hung-Che Ting
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Publication number: 20140198473Abstract: An assembly for mounting a display device in a vehicle. The assembly includes a mounting plate having opposite edges, a front surface extending therebetween, and a rear surface opposite the front surface. The mounting plate is mountable to the vehicle with the front surface of the mounting plate facing outward. The assembly includes a first locking mechanism disposed proximate one edge of the mounting plate and a second locking mechanism disposed proximate the other edge. Each locking mechanism includes a jaw extending over the front surface of the mounting plate and pivotable between closed and open positions. Each jaw includes a resiliently deformable biasing member connected to the jaw and biasing the jaw towards the closed position. The assembly includes an electrical connector attached to the mounting plate.Type: ApplicationFiled: December 11, 2013Publication date: July 17, 2014Applicant: PANASONIC AVIONICS CORPORATIONInventors: Shrenik Shah, Chi-Wei Chou
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Patent number: 8759165Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.Type: GrantFiled: January 15, 2014Date of Patent: June 24, 2014Assignee: AU Optronics Corp.Inventors: Hui-Ling Ku, Chia-Yu Chen, Yi-Chen Chung, Yu-Hung Chen, Chi-Wei Chou, Fan-Wei Chang, Hsueh-Hsing Lu, Hung-Che Ting
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Publication number: 20140127844Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.Type: ApplicationFiled: January 15, 2014Publication date: May 8, 2014Applicant: AU Optronics Corp.Inventors: Hui-Ling Ku, Chia-Yu Chen, Yi-Chen Chung, Yu-Hung Chen, Chi-Wei Chou, Fan-Wei Chang, Hsueh-Hsing Lu, Hung-Che Ting
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Patent number: 8674365Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.Type: GrantFiled: November 5, 2012Date of Patent: March 18, 2014Assignee: AU Optronics Corp.Inventors: Hui-Ling Ku, Chia-Yu Chen, Yi-Chen Chung, Yu-Hung Chen, Chi-Wei Chou, Fan-Wei Chang, Hsueh-Hsing Lu, Hung-Che Ting
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Publication number: 20130134425Abstract: A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.Type: ApplicationFiled: September 14, 2012Publication date: May 30, 2013Applicant: AU OPTRONICS CORP.Inventors: Yi-Chen Chung, Chia-Yu Chen, Hui-Ling Ku, Yu-Hung Chen, Chi-Wei Chou, Fan-Wei Chang, Hsueh-Hsing Lu, Hung-Che Ting
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Publication number: 20020182860Abstract: A method of forming self-aligned silicide layers on semiconductor devices. The method includes a metal sputtering step which sputters a metal material onto a semiconductor device in an environment with a temperature of at least 400° C., an etching step which selectively removes unreacted metal and reacted metal remainder, and a high temperature annealing step which forms a self-aligned silicide layer by rapidly raising the temperature and annealing. Using this method, an inter-mediate can be formed during the metal sputtering process. Therefore, the invention takes out one rapid thermal annealing process in the self-aligned silicide process, reducing the cycle time and cost, and increasing the yield.Type: ApplicationFiled: May 29, 2001Publication date: December 5, 2002Inventors: Cheng-Kuo Yuan, Chi-Wei Chou, Jerry Lin
