Patents by Inventor Chi-Wei Ting

Chi-Wei Ting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240133949
    Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 25, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Lin Yang, Chin-Wei Lin, Po-Chao Tsao, Tung-Hsing Lee, Chia-Jung Ni, Chi-Ming Lee, Yi-Ju Ting
  • Patent number: 11448689
    Abstract: An electronic device, a signal validator, and a method for signal validation are provided. The electronic device includes a circuit board generating a plurality of signals and a signal validator. The signal validator records a current voltage level of each signal as a sequence code and records a time interval between the sequence code and a previous sequence code as a delay time corresponding to the sequence code when a voltage level of one of the plurality of signals changes. The signal validator sequentially determines whether the sequence code matches with a prearranged sequence code. When the sequence code matches with the prearranged sequence code, the signal validator determines whether each delay time corresponding to each sequence code exceeds a predetermined delay time. When the delay time is less than the predetermined delay time, the signal validator determines that the plurality of signals passes signal validation.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: September 20, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Yi-Tso Chang, Chi-Wei Ting
  • Publication number: 20200363467
    Abstract: An electronic device, a signal validator, and a method for signal validation are provided. The electronic device includes a circuit board generating a plurality of signals and a signal validator. The signal validator records a current voltage level of each signal as a sequence code and records a time interval between the sequence code and a previous sequence code as a delay time corresponding to the sequence code when a voltage level of one of the plurality of signals changes. The signal validator sequentially determines whether the sequence code matches with a prearranged sequence code. When the sequence code matches with the prearranged sequence code, the signal validator determines whether each delay time corresponding to each sequence code exceeds a predetermined delay time. When the delay time is less than the predetermined delay time, the signal validator determines that the plurality of signals passes signal validation.
    Type: Application
    Filed: March 4, 2020
    Publication date: November 19, 2020
    Applicant: PEGATRON CORPORATION
    Inventors: YI-TSO CHANG, Chi-Wei Ting