Abstract: A method includes forming first and second gate stacks extending across a semiconductor fin on a substrate; forming source/drain regions in the semiconductor fin, wherein one of the source/drain region is between the first and second gate stacks; forming a dielectric layer laterally surrounding the first and second gate stacks; doping a portion of the dielectric layer between the first and second gate stacks with a dopant; removing the second gate stack to form a gate trench next to the doped first portion of the dielectric layer; performing an annealing process to expand the doped first portion of the dielectric layer toward the gate trench; forming an isolation structure in the gate trench and next to the expanded first portion of the dielectric layer; forming a source/drain contact extending through the dielectric layer to the one of the source/drain regions.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes first nanostructures formed over a substrate along a first direction, and second nanostructures formed over the substrate along the first direction. The semiconductor structure includes a first gate structure formed over the first nanostructures along a second direction, and a second gate structure formed over the second nanostructures along the second direction. The semiconductor structure also includes a dielectric wall structure between the first gate structure and the second gate structure along the second direction. The dielectric wall structure includes a top portion and a bottom portion, and a top width of a top surface of the top portion is smaller than a bottom width of a bottom surface of the bottom portion of the dielectric wall structure.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first active region and a second active region, forming a first n-type work function layer and a first p-type work function layer along the first active region and the second active region, respectively, forming a semiconductor material along the first n-type work function layer and the first p-type work function layer, removing a first portion of the semiconductor material along the first p-type work function layer, thereby leaving a second portion of the semiconductor material as a first protection layer over the first n-type work function layer, and diffusing a dopant into the first p-type work function layer to form a doped p-type work function layer while the first protection layer blocks the dopant from diffusing into the first n-type work function layer.

Abstract: A semiconductor device includes a silicon substrate and a fin formed above the substrate. The fin provides active regions for two devices, such as gate-all-around transistors. The semiconductor device also includes a fin-insulating structure positioned to electrically isolate the active regions for the two devices. The fin-insulating structure is formed in a trench, with a first portion adjacent the fin and a second portion below the fin and extending into the substrate. The fin-insulating structure includes an oxide liner in the second portion of the trench, but not the first portion. The fin-insulating structure is further filled with an insulating material such as silicon nitride.

Abstract: A semiconductor device includes a silicon substrate and a fin formed above the substrate. The fin provides active regions for two devices, such as gate-all-around transistors. The semiconductor device also includes a fin-insulating structure positioned to electrically isolate the active regions for the two devices. The fin-insulating structure is formed in a trench, with a first portion adjacent the fin and a second portion below the fin and extending into the substrate. The fin-insulating structure includes an oxide liner in the second portion of the trench, but not the first portion. The fin-insulating structure is further filled with an insulating material such as silicon nitride.

Abstract: An IC structure and a method of forming the same are provided. In an embodiment, an exemplary method of forming the IC structure forming a first semiconductor fin and a second semiconductor fin protruding from a substrate, forming a high-k metal gate (HKMG) structure over the first semiconductor fin and the second semiconductor fin, forming a trench to separate the HKMG structure into two portions, conformally depositing a first dielectric layer in the trench, depositing a second dielectric layer over the first dielectric layer to fill the trench, wherein the second dielectric layer includes nitrogen, and the first dielectric layer is free of nitrogen, and planarizing the first dielectric layer and second dielectric layer to form a gate isolation structure in the trench.

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming first fin structures and a second fin structures over a substrate, forming a first gate stack and a second gate stack that extend in a first direction across the first fin structures and the second fin structures, respectively, and etching the first gate stack and the second gate stack to form a first trench through the first gate stack and a second trench through the second gate stack. A first dimension of the first trench in the first direction is greater than a second dimension of the second trench in the first direction. The method further includes forming a first gate cutting structure and a second gate cutting structure in the first trench and the second trench, respectively.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a workpiece including a first semiconductor fin and a second semiconductor fin penetrating from a substrate and separated by a first isolation feature, and a gate structure intersecting the first semiconductor fin and the second semiconductor fin. The method also includes removing the gate structure and portions of the first semiconductor fin, the second semiconductor fin, and the first isolation feature disposed directly under the gate structure to form a fin isolation trench, forming a dielectric layer over the workpiece to substantially fill the fin isolation trench, and planarizing the dielectric layer to form a fin isolation structure in the fin isolation trench.

Abstract: A method includes forming first and second gate stacks extending across a semiconductor fin on a substrate; forming source/drain regions in the semiconductor fin, wherein one of the source/drain region is between the first and second gate stacks; forming a dielectric layer laterally surrounding the first and second gate stacks; doping a portion of the dielectric layer between the first and second gate stacks with a dopant; removing the second gate stack to form a gate trench next to the doped first portion of the dielectric layer; performing an annealing process to expand the doped first portion of the dielectric layer toward the gate trench; forming an isolation structure in the gate trench and next to the expanded first portion of the dielectric layer; forming a source/drain contact extending through the dielectric layer to the one of the source/drain regions.

Abstract: A semiconductor device includes a silicon substrate and a fin formed above the substrate. The fin provides active regions for two devices, such as gate-all-around transistors. The semiconductor device also includes a fin-insulating structure positioned to electrically isolate the active regions for the two devices. The fin-insulating structure is formed in a trench, with a first portion adjacent the fin and a second portion below the fin and extending into the substrate. The fin-insulating structure includes an oxide liner in the second portion of the trench, but not the first portion. The fin-insulating structure is further filled with an insulating material such as silicon nitride.

Abstract: A semiconductor device includes a substrate, a shallow trench isolation (STI) structure, a first source/drain, a second source/drain, and an isolation dielectric. The substrate has a semiconductor fin. The STI structure surrounds the semiconductor fin. The first source/drain is embedded in the semiconductor fin. The second source/drain is embedded in the semiconductor fin. The isolation dielectric is between the first and second source/drains and extending into the semiconductor fin. An upper surface of the STI structure is free from coverage of the isolation dielectric.

Abstract: A semiconductor device includes a substrate, a shallow trench isolation (STI) structure, a first source/drain, a second source/drain, and an isolation dielectric. The substrate has a semiconductor fin. The STI structure surrounds the semiconductor fin. The first source/drain is embedded in the semiconductor fin. The second source/drain is embedded in the semiconductor fin. The isolation dielectric is between the first and second source/drains and extending into the semiconductor fin. An upper surface of the STI structure is free from coverage of the isolation dielectric.

Abstract: A slide rail assembly includes first and second rails, a stop, a first engaging member, and a first releasing member. The second rail can be displaced between a retracted position and an extended position with respect to the first rail. The stop is located at the first rail. The first engaging member, movably connected to the second rail, is at an engaged position with respect to the stop when the second rail is at the retracted position with respect to the first rail. The first releasing member is configured to operatively drive the first engaging member away from the engaged position so that the second rail can be displaced from the retracted position toward the extended position with respect to the first rail.

Abstract: A slide rail assembly includes a supporting rail, a first rail, a second rail, and an interlock device. The second rail can be displaced with respect to the first rail. The interlock device is movably disposed between the first rail and the supporting rail. The second rail displaces the interlock device while being displaced from a retracted position with respect to the first rail to a predetermined position in an opening direction.

Abstract: A slide rail assembly includes a first rail, a second rail, a first engagement element, and a second engagement element. The first rail includes a first blocking part. The second rail is movably connected to the first rail. The first and second engagement elements are connected to the second rail. When the second rail moves relative to the first rail toward a first position, the first engagement element abuts against the blocking part of the first rail. When the first engagement element is operatively detached from the blocking part of the first rail, the second rail to is able to move relative to the first rail toward a second position from the first position. When the second rail is located at the second position, at least part of the second engagement element is adjacent to the blocking part of the first rail.

Abstract: A slide rail assembly includes first and second rails, a stop, a first engaging member, and a first releasing member. The second rail can be displaced between a retracted position and an extended position with respect to the first rail. The stop is located at the first rail. The first engaging member, movably connected to the second rail, is at an engaged position with respect to the stop when the second rail is at the retracted position with respect to the first rail. The first releasing member is configured to operatively drive the first engaging member away from the engaged position so that the second rail can be displaced from the retracted position toward the extended position with respect to the first rail.

Abstract: A slide rail assembly includes a supporting rail, a first rail, a second rail, and an interlock device. The second rail can be displaced with respect to the first rail. The interlock device is movably disposed between the first rail and the supporting rail. The second rail displaces the interlock device while being displaced from a retracted position with respect to the first rail to a predetermined position in an opening direction.

Abstract: A slide rail assembly includes a first rail, a second rail, a first engagement element, and a second engagement element. The first rail includes a first blocking part. The second rail is movably connected to the first rail. The first and second engagement elements are connected to the second rail. When the second rail moves relative to the first rail toward a first position, the first engagement element abuts against the blocking part of the first rail. When the first engagement element is operatively detached from the blocking part of the first rail, the second rail to is able to move relative to the first rail toward a second position from the first position. When the second rail is located at the second position, at least part of the second engagement element is adjacent to the blocking part of the first rail.

Abstract: A cable management arm (CMA) for arranging cables extending from at least two areas of an electronic equipment chassis includes first and second cable management mechanisms and first and second supporting mechanisms. The first cable management mechanism serves to arrange cables extending from one of the chassis areas and includes a supporting bracket. The first supporting mechanism serves to support the first cable management mechanism and includes a fastener. The second cable management mechanism serves to arrange cables extending from the other chassis area and includes a supporting bracket releasably mounted to the fastener of the first supporting mechanism. The second supporting mechanism serves to support the second cable management mechanism and includes a fastener releasably mounted to the supporting bracket of the first cable management mechanism.