Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Abstract: A method for making a semiconductor device includes forming a first fin structure, a second fin structure, and a third fin structure over a substrate. The first through third fin structures all extend along a first lateral direction, and the second fin structure is disposed between the first and third fin structures. The method includes forming a mold by filling up trenches between neighboring ones of the first through third fin structures with a first dielectric material. The method includes cutting the second fin structure by removing an upper portion of the second fin structure. The method includes replacing the upper portion of the second fin structure with a second dielectric material to form a dielectric cut structure. The method includes recessing the mold to expose upper portions of the first fin structure and the third fin structure, respectively.

Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Abstract: A method for making a semiconductor device includes forming a first fin structure, a second fin structure, and a third fin structure over a substrate. The first through third fin structures all extend along a first lateral direction, and the second fin structure is disposed between the first and third fin structures. The method includes forming a mold by filling up trenches between neighboring ones of the first through third fin structures with a first dielectric material. The method includes cutting the second fin structure by removing an upper portion of the second fin structure. The method includes replacing the upper portion of the second fin structure with a second dielectric material to form a dielectric cut structure. The method includes recessing the mold to expose upper portions of the first fin structure and the third fin structure, respectively.

Abstract: A neural network (NN) processing unit includes an operation circuit to perform tensor operations of a given layer of a neural network in one of a first number representation and a second number representation. The NN processing unit further includes a conversion circuit coupled to at least one of an input port and an output port of the operation circuit to convert between the first number representation and the second number representation. The first number representation is one of a fixed-point number representation and a floating-point number representation, and the second number representation is the other one of the fixed-point number representation and the floating-point number representation.

Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Abstract: An electronic device has a processing system and a management circuit. The processing system executes an application. The management circuit detects an operating behavior of the application during execution of the application, analyzes the detected operating behavior of the application to generate an application identification result, and configures an application-dependent task according to at least the application identification result.

Abstract: Disclosed is a safety alert apparatus, comprising a communication module to connect a communication network, a detection module including an activity detector and a determination module to determine an emergency event, according to an activity detection signal generated by the activity detector, and to provide an alert signal to the communication module, when an emergency event is determined, such that the communication module provides emergency alerts to a predetermined remote device; wherein the activity detector comprises an electrical appliance remote controller signal detector and uses a wireless channel signal of the electrical appliance remote controller as the activity detection signal.

Abstract: The present invention provides a thermal control method and a thermal control system. The thermal control method comprises: detecting a temperature variance of a component of the electronic device to generate a detecting result; and determining a temperature threshold value for the integrated circuit as a throttling point according to the detecting result. The thermal control system comprises: a detecting unit, for detecting a temperature variance of a component of the electronic device to generate a detecting result; and a determining unit, for determining a temperature threshold value for the integrated circuit as a throttling point according to the detecting result.

Abstract: The present invention provides a thermal control method and a thermal control system. The thermal control method comprises: detecting a temperature variance of a component of the electronic device to generate a detecting result; and determining a temperature threshold value for the integrated circuit as a throttling point according to the detecting result. The thermal control system comprises: a detecting unit, for detecting a temperature variance of a component of the electronic device to generate a detecting result; and a determining unit, for determining a temperature threshold value for the integrated circuit as a throttling point according to the detecting result.

Abstract: An electronic device has a processing system and a management circuit. The processing system executes an application. The management circuit detects an operating behavior of the application during execution of the application, analyzes the detected operating behavior of the application to generate an application identification result, and configures an application-dependent task according to at least the application identification result.

Abstract: Disclosed is a safety alert apparatus, comprising a communication module to connect a communication network, a detection module including an activity detector and a determination module to determine an emergency event, according to an activity detection signal generated by the activity detector, and to provide an alert signal to the communication module, when an emergency event is determined, such that the communication module provides emergency alerts to a predetermined remote device; wherein the activity detector comprises an electrical appliance remote controller signal detector and uses a wireless channel signal of the electrical appliance remote controller as the activity detection signal.

Abstract: An apparatus for processing a video signal with N frames is provided. The apparatus includes an encoding module and a selecting module. The encoding module performs a 1st through a Nth encoding procedure. The 1st through the Nth encoding procedure respectively encodes the 1st through the Nth frame among the N frames in a full-image-encoding mode, encodes other frames in an adaptive-image-encoding mode, and calculates the data amount of the N encoded frames in each encoding procedure, respectively. The selecting module selects the N encoded frames with the smallest data amount among the encoding procedures been performed.

Abstract: An expanding high speed transport interface hardware method for motherboard is provided. In the method, a mezzanine card is provided and the mezzanine card has a chip socket. An expanding hardware with high speed transport interface is installed in the chip socket of the mezzanine card. In addition, the mezzanine card is inserted into an idle CPU socket in a motherboard with plural CPU structure to make the mezzanine card electrically connect with the second CPU socket, so that the mezzanine card and the expanding hardware become components of the motherboard. Finally, the motherboard is activated to detect the mezzanine card and the expanding hardware and set the CPU bus as a data transmission path between the mezzanine card and the expanding hardware so as to expand interface hardware for the idle CPU socket. Besides, more design choices and opportunities are provided for the manufacturers of motherboard and peripheral.

Abstract: An expanding high speed transport interface hardware method for motherboard is provided. In the method, a mezzanine card is provided and the mezzanine card has a chip socket. An expanding hardware with high speed transport interface is installed in the chip socket of the mezzanine card. In addition, the mezzanine card is inserted into an idle CPU socket in a motherboard with plural CPU structure to make the mezzanine card electrically connect with the second CPU socket, so that the mezzanine card and the expanding hardware become components of the motherboard. Finally, the motherboard is activated to detect the mezzanine card and the expanding hardware and set the CPU bus as a data transmission path between the mezzanine card and the expanding hardware so as to expand interface hardware for the idle CPU socket. Besides, more design choices and opportunities are provided for the manufacturers of motherboard and peripheral.

Abstract: Disclosed is a PCI mezzanine card (PMC) with pin-grid-array (PGA) which can be applied onto a two or more central processing unit (CPU) socket equipped mother board When one of the CPU sockets is not installed with a CPU, the PMC communicates with the mother board through the CPU socket with its PGA interface. An IC package mounted on the PMC can communicate with the mother board through the PMC.