Patents by Inventor Chi-Wen Liu

Chi-Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11532500
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Publication number: 20220392663
    Abstract: The present invention relates to a coating process and a process system for a cable, and a cable manufactured thereby. The process includes: (1) providing the cable; (2) transporting the cable into immersion device, the cable immerged in first solution to form first coating layer thereon; (3) transporting the cable out of the immersion; (4) transporting the cable into coating device through third wire die, the cable immerged in second solution to form second coating layer thereon, the second layer is attached to the cable through the first layer; (5) transporting the cable out of the coating device through fourth wire die, fourth aperture diameter of the fourth wire die is larger than third aperture diameter of the third wire die; and (6) heating the cable to cure the second coating layer. The system includes: a cable providing device; an immersion device; a coating device; and a heating device.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 8, 2022
    Inventors: Shi-Wen Huang, Yang Zhou, Cheng Hao, Chi-Wan Huang, Wen-Hsiang Han, Wen-Cheng Wu, Xiao-Yong Liu, Jie Zhang
  • Publication number: 20220392876
    Abstract: A light-emitting device includes a first carrier, which includes a side surface between a first surface and a second surface, upper conductive pads on the first surface, and lower conductive pads under the second surface; a RDL pixel package includes a RDL which includes bonding pads and bottom electrodes, and the light-emitting units on the RDL, and connected to the bonding pads. A light-transmitting layer on the RDL and covers the light-emitting units, an upper surface, a lower surface, and a lateral surface between the upper surface and the lower surface. The RDL pixel package is on the first surface and electrically connected to the upper conductive pads. A protective layer covers the first surface and contacting the side surface of the RDL pixel package. The lower electrodes and the upper conductive pads are connected, and the distance between two adjacent bonding pads is less than 30 ?m.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 8, 2022
    Inventors: Min-Hsun HSIEH, Hsin-Mao LIU, Li-Yuan HUANG, Tzu-Hsiang WANG, Chi-Chih PU, Ya-Wen LIN, Hsiao-Pei CHIU, Pei-Yu LI
  • Publication number: 20220352329
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • Publication number: 20220344274
    Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.
    Type: Application
    Filed: July 11, 2022
    Publication date: October 27, 2022
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Publication number: 20220310826
    Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.
    Type: Application
    Filed: June 16, 2022
    Publication date: September 29, 2022
    Inventors: Kuo-Cheng Chiang, Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung
  • Publication number: 20220310593
    Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin structure is formed on the substrate. A first semiconductor material is formed on both the first fin structure and the second fin structure. A second semiconductor material is formed on the first semiconductor material on both the first fin structure and the second fin structure. The first semiconductor material on the first fin structure is oxidized to form a first oxide. The second semiconductor material on the first fin structure is removed. A first dielectric material and a first electrode are formed on the first fin structure. A second dielectric material and a second electrode are formed on the second fin structure.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Inventors: Chi-Wen LIU, Chao-Hsiung WANG
  • Publication number: 20220302257
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 11437479
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • Publication number: 20220271165
    Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.
    Type: Application
    Filed: May 13, 2022
    Publication date: August 25, 2022
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • Patent number: 11425827
    Abstract: A foldable electronic device including a first body, a second body, a flexible display disposed on the first and the second bodies, a hinge assembly connected between the first and the second bodies, an extension chain assembly, and a linkage is provided. The first and the second bodies are rotated relatively to be unfolded or folded via the hinge assembly. An end of the linkage and an end of the extension chain assembly are pivoted together and coupled to the first body in a sliding and pivoting manner. Another end of the linkage is pivoted to the hinge assembly, and another end of the extension chain assembly is pivoted to the second body. In a transforming process between the folded and the unfolded states, an extension traveling of the extension chain assembly compensates a size difference of the flexible display between the folded and the unfolded states.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: August 23, 2022
    Assignee: Acer Incorporated
    Inventors: Ting-Wen Pai, Chi-Hung Lai, Wu-Chen Lee, Chih-Chun Liu
  • Patent number: 11404376
    Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Publication number: 20220216301
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 11362087
    Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin structure is formed on the substrate. A first semiconductor material is formed on both the first fin structure and the second fin structure. A second semiconductor material is formed on the first semiconductor material on both the first fin structure and the second fin structure. The first semiconductor material on the first fin structure is oxidized to form a first oxide. The second semiconductor material on the first fin structure is removed. A first dielectric material and a first electrode are formed on the first fin structure. A second dielectric material and a second electrode are formed on the second fin structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 11362004
    Abstract: In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu
  • Patent number: 11335809
    Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • Patent number: 11309385
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20220045214
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • Patent number: 11211498
    Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang, Ying-Keung Leung
  • Patent number: 11205594
    Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Ting-Hung Hsu, Chao-Hsiung Wang, Chi-Wen Liu