Patents by Inventor Chi-Wen Liu

Chi-Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vertical Gate All Around (VGAA) Devices and Methods of Manufacturing the Same
    Publication number: 20160240378
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: forming a first doped region having a first conductivity in a substrate; forming a second doped region having a second conductivity different from the first conductivity in the substrate, the second doped region disposed laterally adjacent to and spaced apart from the first doped region; and oxidizing a semiconductive layer disposed between the substrate and the second doped region to form an oxidized isolation layer.
    Type: Application
    Filed: March 6, 2015
    Publication date: August 18, 2016
    Inventors: Yu-Lien Huang, Chun-Hsiung Lin, Chi-Wen Liu
  • Wrap around silicide for FinFETs
    Patent number: 9418897
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu, Ying-Keung Leung
  • Integrated Circuit Having a MOM Capacitor and Method of Making Same
    Publication number: 20160233213
    Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.
    Type: Application
    Filed: April 18, 2016
    Publication date: August 11, 2016
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR SHEET UNIT INTERCONNECTING A SOURCE AND A DRAIN
    Publication number: 20160233302
    Abstract: A semiconductor device includes a substrate, a pair of source/drain units, and a semiconductor sheet unit. The substrate includes a well region. The source/drain units are disposed above the well region. The semiconductor sheet unit is disposed substantially vertically, interconnects the source/drain units, and defines a cross-sectional shape unit in a top view. The cross-sectional shape unit includes a plurality of cross-sections that have substantially the same shape and different sizes.
    Type: Application
    Filed: April 19, 2016
    Publication date: August 11, 2016
    Inventors: JIUN-PENG WU, TETSU OHTOU, CHING-WEI TSAI, CHIH-HAO WANG, CHI-WEN LIU
  • FinFET with Dummy Gate on Non-Recessed Shallow Trench Isolation (STI)
    Publication number: 20160233133
    Abstract: An embodiment fin field effect transistor (FinFET) device includes fins formed from a semiconductor substrate, a non-recessed shallow trench isolation (STI) region disposed between the fins, and a dummy gate disposed on the non-recessed STI region.
    Type: Application
    Filed: April 18, 2016
    Publication date: August 11, 2016
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Multi-Fin Device and Method of Making Same
    Publication number: 20160225765
    Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.
    Type: Application
    Filed: April 11, 2016
    Publication date: August 4, 2016
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Method and structure for vertical tunneling field effect transistor and planar devices
    Patent number: 9406669
    Abstract: The present disclosure provides one embodiment of a method of forming a tunnel field effect transistor (TFET). The method includes forming a semiconductor mesa on a semiconductor substrate; performing a first implantation to the semiconductor substrate and the semiconductor mesa to form a drain of a first type conductivity; forming a first dielectric layer on the semiconductor substrate and sidewall of the semiconductor mesa; forming a gate stack on the sidewall of the semiconductor mesa and the first dielectric layer; forming a second dielectric layer on the first dielectric layer and the gate stack; and forming, on the semiconductor mesa, a source having a second type conductivity opposite to the first type conductivity. The gate stack includes a gate dielectric and a gate electrode on the gate dielectric. The source, drain and gate stack are configured to form the TFET.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Chao-Hsiung Wang, Ming Zhu
  • FinFET Structure with Different Fin Heights and Method for Forming the Same
    Publication number: 20160211138
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Application
    Filed: March 30, 2016
    Publication date: July 21, 2016
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Silicide region of gate-all-around transistor
    Patent number: 9397159
    Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a nanowire structure protruding from the substrate comprising a channel region between a source region and a drain region; a pair of silicide regions extending into opposite sides of the source region, wherein each of the pair of silicide regions comprising a vertical portion adjacent to the source region and a horizontal portion adjacent to the substrate; and a metal gate surrounding a portion the channel region.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu, Chao-Hsiung Wang
  • Contact Etch Stop Layers of a Field Effect Transistor
    Publication number: 20160204026
    Abstract: A representative method for fabricating a field effect transistor comprises forming a source region and a drain region disposed in a substrate; forming a gate structure over the substrate, the gate structure comprising sidewalls and a top surface, the gate structure interposing the source region and the drain region; forming a contact etch stop layer (CESL) over at least a portion of the top surface of the gate structure; forming an interlayer dielectric layer over the CESL; forming a gate contact extending through the interlayer dielectric layer; and forming a source contact and a drain contact extending through the interlayer dielectric layer, wherein a first distance between an edge of the source contact and a first corresponding edge of the CESL is about 1 nm to about 10 nm.
    Type: Application
    Filed: March 24, 2016
    Publication date: July 14, 2016
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Gate contact structure for FinFET
    Patent number: 9385069
    Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • FinFETs with strained well regions
    Patent number: 9385234
    Abstract: A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Chi-Wen Liu
  • Contact structure of semiconductor device
    Patent number: 9379108
    Abstract: A method of fabricating a semiconductor device comprises forming a fin structure extending from a substrate, the fin structure comprising a first fin, a second fin, and a third fin between the first fin and the second fin. The method further comprises forming germanide over a first facet of the first fin, a second facet of the second fin, and a substantially planar surface of the third fin, wherein the first facet forms a first acute angle with a major surface of the substrate and is substantially mirror symmetric with the second facet, and wherein the substantially planar surface of the third fin forms a second acute angle smaller than the first acute angle with the major surface of the substrate.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Wen Liu, Chi-Yuan Shih, Li-Chi Yu, Meng-Chun Chang, Ting-Chu Ko, Chung-Hsien Chen
  • Isolation Structure of Fin Field Effect Transistor
    Publication number: 20160172470
    Abstract: A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.
    Type: Application
    Filed: February 5, 2016
    Publication date: June 16, 2016
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • FETs and methods for forming the same
    Patent number: 9362386
    Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee, Chi-Wen Liu
  • Passivated and Faceted for Fin Field Effect Transistor
    Publication number: 20160155846
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Application
    Filed: February 8, 2016
    Publication date: June 2, 2016
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • FinFETs and methods for forming the same
    Patent number: 9349841
    Abstract: A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tsu-Hsiu Perng, Chi-Kang Liu, Yung-Ta Li, Ming-Huan Tsai, Clement Hsingjen Wann, Chi-Wen Liu
  • Metal gate stack having TaAlCN layer
    Patent number: 9337192
    Abstract: An integrated circuit device includes a semiconductor substrate; and a gate stack disposed over the semiconductor substrate. The gate stack further includes a gate dielectric layer disposed over the semiconductor substrate; a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer comprises tantalum aluminum carbon nitride (TaAlCN); a work function layer disposed over the multi-function blocking/wetting layer; and a conductive layer disposed over the work function layer.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko Jangjian, Ting-Chun Wang, Chi-Cherng Jeng, Chi-Wen Liu
  • Metal gate stack having TiAICN as work function layer and/or blocking/wetting layer
    Patent number: 9337303
    Abstract: A metal gate stack having a titanium aluminum carbon nitride (TiAlCN) as a work function layer and/or a multi-function blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate, a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer includes TiAlCN, a work function layer disposed over the multi-function blocking/wetting layer, and a conductive layer disposed over the work function layer.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko Jangjian, Chi-Wen Liu, Chi-Cherng Jeng, Ting-Chun Wang
  • FinFET with dummy gate on non-recessed shallow trench isolation (STI)
    Patent number: 9337318
    Abstract: An embodiment fin field effect transistor (FinFET) device includes fins formed from a semiconductor substrate, a non-recessed shallow trench isolation (STI) region disposed between the fins, and a dummy gate disposed on the non-recessed STI region.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang