Patents by Inventor Chi-Wen Yao

Chi-Wen Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7704890
    Abstract: A method for fabricating a TFT is provided. First, a poly-silicon layer is formed over a substrate. A photoresist layer is formed on the poly-silicon layer, wherein the photoresist layer has a pattern for exposing parts of the poly-silicon layer, and the pattern has a varied thickness. The poly-silicon layer is patterned by using the photoresist layer as an etching mask to define a poly-silicon island. Thereafter, a part of the thickness of the photoresist layer is removed for exposing a part of the poly-silicon island. Then, a first ion implanting is performed on the exposed part of the poly-silicon island to form a source and a drain thereby. After removing the residue photoresist layer; a gate insulating layer, a gate, a patterned dielectric layer and a conductive layer are formed on the substrate sequentially.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: April 27, 2010
    Assignee: AU Optronics Corp.
    Inventor: Chi-Wen Yao
  • Patent number: 7585712
    Abstract: A method of fabricating a TFT array substrate and a metal layer thereof is provided. First, a substrate having a first patterned metal layer disposed thereon is provided, wherein the first patterned metal layer is formed by an electroplating method. Then, a gate insulating layer is formed on the substrate, wherein the gate insulating layer covers the first metal layer. Next, a semiconductive layer is formed on the gate insulating layer over the first metal layer. Then, a patterned second metal layer is formed on the semiconductive layer. The first metal layer, the second metal layer and the semiconductive layer constitute a plurality of thin film transistors, a plurality of scanning lines and a plurality of data lines, wherein the scanning lines and the data lines are coupled to the thin film transistors.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: September 8, 2009
    Assignee: Au Optronics Corp.
    Inventors: Chi-Wen Yao, Pei-Hsin Yu
  • Publication number: 20070153170
    Abstract: A method of fabricating a pixel structure is provided. A scan line, a data line and an active device electrically connected to the scan line and the data line are formed over a substrate. A dielectric layer is formed over the substrate, and then a patterned photoresist layer is formed thereon. The patterned photoresist layer has first recesses and a first through hole that exposes a portion of the dielectric layer. A portion of the dielectric layer is removed using the patterned photoresist layer as an etching mask to form a patterned dielectric layer. The patterned dielectric has second recesses and a second through hole that exposes a portion of the active device. The patterned photoresist layer is removed and a reflective layer is formed on the patterned dielectric layer. The reflective layer covers the second recesses and electrically connects to the active device.
    Type: Application
    Filed: April 19, 2006
    Publication date: July 5, 2007
    Inventor: Chi-Wen Yao
  • Publication number: 20070132902
    Abstract: A LCD is disclosed, including a gate line formed on an insulating substrate with a segment having one side protruding to form a protrusion region and an indentation region facing the protrusion region, an active layer formed on the segment of the gate line, a pixel electrode formed on the protruding side of the segment, a source line extending substantially perpendicular to the gate line to cross the overlapped region of the active layer and the gate line and prolonging beyond the edges of the active layer, and a drain line coupled to the pixel electrode and extending substantially parallel to the source line to cross the overlapped region of the active layer and the gate line The LCD is capable of preventing deviation in gate-drain parasitic capacitance to reduce difference in luminance between divisional exposure regions. The invention further discloses a method for manufacturing the same.
    Type: Application
    Filed: July 11, 2006
    Publication date: June 14, 2007
    Applicant: QUANTA DISPLAY INC.
    Inventor: Chi-Wen Yao
  • Publication number: 20070026347
    Abstract: A method for fabricating a TFT is provided. First, a poly-silicon layer is formed over a substrate. A photoresist layer is formed on the poly-silicon layer, wherein the photoresist layer has a pattern for exposing parts of the poly-silicon layer, and the pattern has a varied thickness. The poly-silicon layer is patterned by using the photoresist layer as an etching mask to define a poly-silicon island. Thereafter, a part of the thickness of the photoresist layer is removed for exposing a part of the poly-silicon island. Then, a first ion implanting is performed on the exposed part of the poly-silicon island to form a source and a drain thereby. After removing the residue photoresist layer; a gate insulating layer, a gate, a patterned dielectric layer and a conductive layer are formed on the substrate sequentially.
    Type: Application
    Filed: June 13, 2006
    Publication date: February 1, 2007
    Inventor: Chi-Wen Yao
  • Publication number: 20060231407
    Abstract: A method of fabricating a TFT array substrate and a metal layer thereof is provided. First, a substrate having a first patterned metal layer disposed thereon is provided, wherein the first patterned metal layer is formed by an electroplating method. Then, a gate insulating layer is formed on the substrate, wherein the gate insulating layer covers the first metal layer. Next, a semiconductive layer is formed on the gate insulating layer over the first metal layer. Then, a patterned second metal layer is formed on the semiconductive layer. The first metal layer, the second metal layer and the semiconductive layer constitute a plurality of thin film transistors, a plurality of scanning lines and a plurality of data lines, wherein the scanning lines and the data lines are coupled to the thin film transistors.
    Type: Application
    Filed: April 14, 2006
    Publication date: October 19, 2006
    Inventors: Chi-Wen Yao, Pei-Hsin Yu