Patents by Inventor Chi-Weon Yoon

Chi-Weon Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11164637
    Abstract: A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit applies an erase voltage to an erase source terminal of the memory block, and applies a first voltage to a first selection line among a plurality of selection lines in the memory block. The first voltage is higher than the erase voltage. The first selection line is disposed closest to the erase source terminal among the plurality of selection lines and is used for selecting the memory block as an erase target block.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 2, 2021
    Inventors: Sang-Wan Nam, Dong-Hun Kwak, Chi-Weon Yoon
  • Patent number: 11074978
    Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: July 27, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hun Kwak, Sang Wan Nam, Chi Weon Yoon
  • Publication number: 20210193679
    Abstract: Provided is a semiconductor memory device. In order to permit dense integration of a high number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor Mary device. The charge pump makes use of a capacitor. The capacitor is implemented with respect to the dense integration. Some components are placed under the stacked word lines, and some are not under the stacked word lines. The capacity of the capacitor not under the stacked word lines is provided in part by a parallel structure.
    Type: Application
    Filed: August 14, 2020
    Publication date: June 24, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Hong KWON, Chan Ho KIM, Kyung Hwa YUN, Dae Seok BYEON, Chi Weon YOON
  • Publication number: 20210117321
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 22, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chi Weon YOON, Dong Hyuk CHAE, Sang-Wan NAM, Jung-Yun YUN
  • Patent number: 10909032
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chi Weon Yoon, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun
  • Patent number: 10892019
    Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: January 12, 2021
    Inventors: Sang-Wan Nam, Dong-Hun Kwak, Chi-Weon Yoon
  • Publication number: 20200411106
    Abstract: A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit applies an erase voltage to an erase source terminal of the memory block, and applies a first voltage to a first selection line among a plurality of selection lines in the memory block. The first voltage is higher than the erase voltage. The first selection line is disposed closest to the erase source terminal among the plurality of selection lines and is used for selecting the memory block as an erase target block.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 31, 2020
    Inventors: Sang-Wan Nam, Dong-Hun Kwak, Chi-Weon Yoon
  • Patent number: 10878919
    Abstract: A method for initializing a channel in a non-volatile memory device comprising a memory block including a plurality of word lines and a plurality of string selection lines, includes applying a voltage to the plurality of string selection lines; converting a bit line passing through the block into a floating state; and a releasing the floating state of the bit line.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Ho Cho, Kyo Man Kang, Dae Seok Byeon, Jung Ho Song, Chi Weon Yoon
  • Publication number: 20200294601
    Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Inventors: Dong Hun KWAK, Sang Wan NAM, Chi Weon YOON
  • Patent number: 10748621
    Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hun Kwak, Sang Wan Nam, Chi Weon Yoon
  • Publication number: 20200242030
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 30, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chi Weon YOON, Dong Hyuk CHAE, Sang-Wan NAM, Jung-Yun YUN
  • Patent number: 10720209
    Abstract: A resistive memory element or device includes: a first, main, memory cell area including a plurality of first resistive memory cells; and a second, buffer, memory cell area including a plurality of second resistive memory cells. The first resistive memory cells of the main memory cell area are configured to store data therein, and the second resistive memory cells of the buffer memory cell area are configured to temporarily store portions of the data therein for at least a stabilization time period while the portions of the data stabilize in the main memory cell area.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Kook Park, Young Hoon Oh, Chi Weon Yoon, Yong Jun Lee, Chea Ouk Lim
  • Publication number: 20200185038
    Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 11, 2020
    Inventors: Sang-Wan Nam, Dong-Hun Kwak, Chi-Weon Yoon
  • Patent number: 10679702
    Abstract: A memory device includes a first memory area, a second memory area, a third memory area and a controller. The first memory area has a plurality of first memory cells sharing a first channel area. The second memory area has a plurality of second memory cells sharing the first channel area. The third memory area having a plurality of third memory cells sharing a second channel area, the second channel area being different from the first channel area, the first channel area and the second channel area being connected to a bit line. The controller is configured to input a voltage for the second memory cells to the second memory cells and a voltage for the third memory cells to the third memory cells, when a controlling operation is performed on the first memory cells, the voltages for the second and third memory cells having different magnitudes.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 9, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hun Kwak, Sang Wan Nam, Chi Weon Yoon
  • Patent number: 10671529
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chi Weon Yoon, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun
  • Publication number: 20200152275
    Abstract: A method for initializing a channel in a non-volatile memory device comprising a memory block including a plurality of word lines and a plurality of string selection lines, includes applying a voltage to the plurality of string selection lines; converting a bit line passing through the block into a floating state; and a releasing the floating state of the bit line.
    Type: Application
    Filed: May 23, 2019
    Publication date: May 14, 2020
    Inventors: DOO HO CHO, KYO MAN KANG, DAE SEOK BYEON, JUNG HO SONG, CHI WEON YOON
  • Patent number: 10600487
    Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Dong-Hun Kwak, Chi-Weon Yoon
  • Patent number: 10566039
    Abstract: A memory device includes a memory cell array including a plurality of word lines, a first string select line above the plurality of word lines, and a second string select line between the first string select line and the plurality of word lines, and a controller. During an operation of reading data of a first memory cell connected to a first word line among the plurality of word lines, the controller is to supply a first voltage to the first string select line and to supply a second voltage to the second string select line, the second voltage being greater than the first voltage.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Wan Nam, Dong Hun Kwak, Wan Dong Kim, Chi Weon Yoon
  • Patent number: 10490289
    Abstract: A voltage generator of a nonvolatile memory device includes a charging circuit, a current mirror circuit, a discharging circuit and an output circuit. The charging circuit amplifies a difference between a reference voltage and a feedback voltage to generate a first current. The current mirror circuit is connected to the charging circuit and generates a second current based on the first current. The discharging circuit is connected to the current mirror circuit to draw the second current, and discharges the output voltage to a target level by adjusting discharging amount of the second current based on a sensing voltage which reflects a change of the feedback voltage. The output circuit is connected to the current mirror circuit, and provides the output voltage based on the first current and the second current to a first word-line connected to an output node.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: November 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyo-Soo Choo, Ji-Hyun Park, Chi-Weon Yoon, Moo-Sung Kim
  • Publication number: 20190279720
    Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.
    Type: Application
    Filed: November 30, 2018
    Publication date: September 12, 2019
    Inventors: Sang-Wan NAM, Dong-Hun KWAK, Chi-Weon YOON