Abstract: A method for programming a flash memory device is provided, where the flash memory device includes a plurality of memory cells, and where a threshold voltage of each of the memory cells is programmable in any one of plural corresponding data states.

Abstract: A flash memory device includes a memory cell array with multiple memory cells, a data buffer, a write driver and a controller. The data buffer stores data to be programmed into the memory cells, the data having sequential data addresses. The write driver programs the data stored in the data buffer into the memory cells during one programming operation. The controller controls operations of the data buffer and the write driver, and performs flexible mapping between addresses of the data buffer and the data addresses based on a first address of the data.

Abstract: A flash memory device includes a memory cell array, an address buffer circuit including address buffers, each address buffer configured to store an address for a random read operation, a read circuit configured to sense data from the memory cell array in response to an address output from the address buffer circuit, an output data latch circuit configured to receive data sensed by the read circuit, and a control logic coupled to the address buffer circuit, the read circuit, and the output data latch circuit, and configured to control the output data latch circuit and the read circuit such that the output data latch circuit outputs first data read from the memory cell array substantially simultaneously as the read circuit senses second data from the memory cell array.

Abstract: Disclosed is a semiconductor memory device which is operable a pipelined-buffer programming and includes a cell array including a plurality of memory cells, a write driver circuit divided into a plurality of write units, each write unit programming memory cells with a first data, a sense amplifier circuit divided into plurality of read units of the same number as the plurality of write units, each read unit sensing bit lines of the cell array during a program verify operation, a selection circuit for selecting one of the write units and one of the read units in response to a column address and a data input circuit for providing the first data to the selected write unit during a program operation and for receiving verifying data from the selected read unit during the program verify operation.

Abstract: An erase operation for a flash memory device includes identifying a sector group including a plurality of sectors based on an address, simultaneously pre-programming the sectors in the sector group, simultaneously erasing the sectors the sector group, and simultaneously post-programming the sectors in the sector group.

Abstract: Disclosed is a frame buffer structure having a sub-word line way of 9 banks in which a dispersed 9-tile mapping shaped data storing method and a partial activation for the method are possible, the frame buffer structure requiring a low power consumption, and a frame buffer being integrated with a logic to properly correspond to an application region to process an MPEG image signal. A method for storing a compressed MPEG image in the frame buffer, comprises: a first step of dividing an image frame into 8×8 pixels regions; a second step of re-designating the respective divided pixel regions into 9 adjacent blocks regions having a form of 3×3; a third step of mapping the 8×8 pixel regions consisting of the 9 adjacent blocks regions having the form of 3×3 into one column; and a fourth step of dispersion-storing the mapped 9 blocks regions of 8×8 pixel regions in different banks.

Abstract: Disclosed is a frame buffer structure having a sub-word line way of 9 banks in which a dispersed 9-tile mapping shaped data storing method and a partial activation for the method are possible, the frame buffer structure requiring a low power consumption, and a frame buffer being integrated with a logic to properly correspond to an application region to process an MPEG image signal. A method for storing a compressed MPEG image in the frame buffer, comprises: a first step of dividing an image frame into 8×8 pixels regions; a second step of re-designating the respective divided pixel regions into 9 adjacent blocks regions having a form of 3×3; a third step of mapping the 8×8 pixel regions consisting of the 9 adjacent blocks regions having the form of 3×3 into one column; and a fourth step of dispersion-storing the mapped 9 blocks regions of 8×8 pixel regions in different banks.

Abstract: A Row-After-Column memory addressing method. The memory addressing method changes the order of addressing so as to enhance the efficiency of memory addressing. The Row-After-Column memory addressing method of the present invention comprises the steps of activating a column path by generating the column address when the address is input for data access, and activating a row path by generating the row address according to the address. Therefore, pipeline stall arising from inputting the column address (/CAS) subsequent to input of the row address (/RAS) can be eliminated and the speed of memory access can be enhanced.

Abstract: A Row-After-Column memory addressing method. The memory addressing method changes the order of addressing so as to enhance the efficiency of memory addressing. The Row-After-Column memory addressing method of the present invention comprises the steps of activating a column path by generating the column address when the address is input for data access, and activating a row path by generating the row address according to the address. Therefore, pipeline stall arising from inputting the column address (/CAS) subsequent to input of the row address (/RAS) can be eliminated and the speed of memory access can be enhanced.