Abstract: A stacked transistor arrangement and process of manufacture thereof are provided. Switched electrodes of first and second transistor chips are accessible on opposite sides of the first and second transistor chips. The first and second transistor chips are stacked one on top of the other. Switched electrodes of adjacent sides of the transistor chips are coupled together by a conductive layer positioned between the first and second transistor chips. Switched electrodes on sides of the first transistor chip and the second transistor chip that are opposite the adjacent sides are coupled to a lead frame by bond wires or solder bumps.

Abstract: Methods for manufacturing a MOSFET device for high voltage application are disclosed to solve less-than-90-degree trench angle problem. In one embodiment, the trenches in a MOSFET device are filled with different concentrations of P? epitaxial material at different stages to improve charge balance. In an alternative embodiment, several N? epitaxial layers with different concentrations are created before etching trenches filled with P? epitaxial material. Yet in another embodiment, a reverse deep trench process creates a P? epitaxial layer first, and etches trenches to be filled with N? epitaxial and act as active region during device operation, leaving the remaining P? epitaxial columns as non-active regions. The final device structure of the remaining P? epitaxial columns is similar to the traditional P? epitaxial trenches.

Abstract: Methods for manufacturing a MOSFET device for high voltage application are disclosed to solve less-than-90-degree trench angle problem. In one embodiment, the trenches in a MOSFET device are filled with different concentrations of P? epitaxial material at different stages to improve charge balance. In an alternative embodiment, several N? epitaxial layers with different concentrations are created before etching trenches filled with P? epitaxial material. Yet in another embodiment, a reverse deep trench process creates a P? epitaxial layer first, and etches wider conductive regions to be filled with N? epitaxial later, leaving the remaining P? epitaxial columns as non-conductive regions similar to the traditional P? epitaxial trenches.