Patents by Inventor Chi-Yao Wang

Chi-Yao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170485
    Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has a U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kun-Yu LEE, Chun-Yao WANG, Chi On CHUI
  • Publication number: 20240082642
    Abstract: An intelligent exercise intensity assessing system includes an exercise testing machine, a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser operates the exercise testing machine. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database. The cloud database analyzes the physiological information to obtain a corresponding forecasted watt value, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 14, 2024
    Applicant: EHUNTSUN HEALTH TECHNOLOGY CO., LTD.
    Inventors: Chao-Chuan CHEN, Han-Pin HO, Jong-Shyan WANG, Yu-Ting LIN, Chi-Yao CHIANG, Yu-Liang LIN
  • Publication number: 20240082640
    Abstract: An exercise intensity assessing system includes a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser exercises. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database for being diagnosed and analyzed by a fitness instructor. The cloud database obtains a forecasted watt value corresponding to the physiological information, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 14, 2024
    Applicant: EHUNTSUN HEALTH TECHNOLOGY CO., LTD.
    Inventors: Chao-Chuan CHEN, Han-Pin HO, Jong-Shyan WANG, Yu-Ting LIN, Chi-Yao CHIANG, Yu-Liang LIN
  • Patent number: 11923360
    Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has an U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kun-Yu Lee, Chun-Yao Wang, Chi On Chui
  • Patent number: 6680474
    Abstract: A semiconductor calibration wafer that has no charge effect is disclosed. The calibration wafer has a substrate layer and a conductive metal layer. The conductive metal layer completely covers the substrate layer, and has a critical dimension (CD) bar corresponding to a desired CD. The substrate layer may be an oxide layer or another type of substrate layer, whereas the conductive metal layer may be an aluminum layer, a copper layer, or another type of conductive metal layer. Where the calibration wafer is used in conjunction with a scanning electron microscope (SEM) to monitor the CD, the electrons ejected by the SEM do not remain on the semiconductor calibration wafer, but instead are carried away via the conductive metal layer. The calibration wafer is thus not vulnerable to the charge effect.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: January 20, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chi-Yao Wang, Ming-Shuo Yen
  • Publication number: 20030132374
    Abstract: A semiconductor calibration wafer that has no charge effect is disclosed. The calibration wafer has a substrate layer and a conductive metal layer. The conductive metal layer completely covers the substrate layer, and has a critical dimension (CD) bar corresponding to a desired CD. The substrate layer may be an oxide layer or another type of substrate layer, whereas the conductive metal layer may be an aluminum layer, a copper layer, or another type of conductive metal layer. Where the calibration wafer is used in conjunction with a scanning electron microscope (SEM) to monitor the CD, the electrons ejected by the SEM do not remain on the semiconductor calibration wafer, but instead are carried away via the conductive metal layer. The calibration wafer is thus not vulnerable to the charge effect.
    Type: Application
    Filed: January 14, 2002
    Publication date: July 17, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Yao Wang, Ming-Shuo Yen