Patents by Inventor Chi-Yen Lin
Chi-Yen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240112924Abstract: An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Hsu-Hsien Chen, Chen-Shien Chen, Ting Hao Kuo, Chi-Yen Lin, Yu-Chih Huang
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Patent number: 11944412Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.Type: GrantFiled: June 2, 2021Date of Patent: April 2, 2024Assignee: MICROJET TECHNOLOGY CO., LTD.Inventors: Hao-Jan Mou, Ying-Lun Chang, Ching-Sung Lin, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee, Chun-Yi Kuo, Tsung-I Lin
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Patent number: 11944935Abstract: A gas detection purification device is disclosed and includes a main body, a purification unit, a gas guider, a gas detection module and a controlling-driving module. The main body includes an inlet, an outlet, an external socket and a gas-flow channel disposed between the inlet and the outlet. The purification unit is disposed in the gas-flow channel for filtering gas introduced through the gas-flow channel. The gas guider is disposed in the gas channel and located at a side of the purification unit. The gas is inhaled through the inlet, flows through the purification unit and is discharged out through the outlet. The gas detection module is plugged into or detached from the external socket. The controlling driving module is disposed within the main body and electrically connected to the gas guider to control the operation of the gas guider in an enabled state and a disabled state.Type: GrantFiled: December 2, 2020Date of Patent: April 2, 2024Assignee: MICROJET TECHNOLOGY CO., LTD.Inventors: Hao-Jan Mou, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai, Wei-Ming Lee, Tsung-I Lin
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Publication number: 20240085766Abstract: This document describes a thermal-control system that is integrated into a security camera. The thermal-control system includes a combination of heatsinks and thermal interface materials with high thermal conductivities. The thermal-control system may transfer and spread energy from a high thermal-loading condition effectuated upon the security camera to concurrently maintain temperatures of multiple thermal zones on or within the security camera at or below prescribed temperature thresholds.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: Google LLCInventors: Ihab A. Ali, Arun Prakash Raghupathy, Mark Benjamin Kraz, Kok Yen Cheng, Chi-Ming Lin
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Publication number: 20240063158Abstract: A method of making a semiconductor structure includes forming a first contact pad over an interconnect structure. The method further includes forming a second contact pad over the interconnect structure, wherein the second contact pad is electrically separated from the first contact pad. The method further includes depositing a first buffer layer over the interconnect structure, wherein the first buffer layer partially covers the second contact pad, and an edge of the second contact pad extends beyond the first buffer layer.Type: ApplicationFiled: November 2, 2023Publication date: February 22, 2024Inventors: Gulbagh SINGH, Chih-Ming LEE, Chi-Yen LIN, Wen-Chang KUO, C. C. LIU
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Patent number: 11810879Abstract: A semiconductor structure includes a first contact pad over an interconnect structure. The semiconductor structure further includes a second contact pad over the interconnect structure, wherein the second contact pad is electrically separated from the first contact pad. The semiconductor structure further includes a first buffer layer over the first contact pad, wherein the first buffer layer is partially over the second contact pad, and an edge of the second contact pad farthest from the first contact pad extends beyond the first buffer layer.Type: GrantFiled: March 18, 2022Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Gulbagh Singh, Chih-Ming Lee, Chi-Yen Lin, Wen-Chang Kuo, C. C. Liu
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Patent number: 11794381Abstract: A laser-debondable composition includes an acrylic resin, a light-shielding material, an additive, and a solvent. Wherein, the acrylic resin includes at least one nitrogen-containing organic group selected from a group consisting of tertiary amino groups and secondary amino groups, an organic group having a cyclic ether group, and an organic group having a hydroxyl group, and the additive includes at least one adhesion promoter. The laser-debondable composition has excellent adhesion ability to a substrate, attachability, and solvent resistance.Type: GrantFiled: January 20, 2021Date of Patent: October 24, 2023Assignee: DAXIN MATERIALS CORPORATIONInventors: Shih-Yun Chiu, Cheng-Wei Lee, Chi-Yen Lin
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Patent number: 11653498Abstract: The present disclosure relates to a memory device that includes a substrate and source and drain regions formed in the substrate. The memory device includes a gate dielectric formed on the substrate and between the source and drain regions. The memory device also includes a gate structure formed on the gate dielectric and the gate structure has a planar top surface. The memory device further includes a multi-spacer structure that includes first, second, and third spacers. The first spacer is formed on a sidewall of the gate structure and a top surface of one of the source and drain regions. The second spacer is formed on a sidewall of the first spacer and the second spacer has a dielectric constant greater than a dielectric constant of the first spacer. The third spacer is formed on a sidewall of the second spacer and a horizontal surface of the first spacer.Type: GrantFiled: July 13, 2018Date of Patent: May 16, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh Singh, Chen-Hao Li, Chih-Ming Lee, Chi-Yen Lin, Cheng-Tsu Liu
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Publication number: 20220415916Abstract: The present disclosure relates to a memory device that includes a substrate and source and drain regions formed in the substrate. The memory device includes a gate dielectric formed on the substrate and between the source and drain regions. The memory device also includes a gate structure formed on the gate dielectric and the gate structure has a planar top surface. The memory device further includes a multi-spacer structure that includes first, second, and third spacers. The first spacer is formed on a sidewall of the gate structure and a top surface of one of the source and drain regions. The second spacer is formed on a sidewall of the first spacer and the second spacer has a dielectric constant greater than a dielectric constant of the first spacer. The third spacer is formed on a sidewall of the second spacer and a horizontal surface of the first spacer.Type: ApplicationFiled: July 28, 2022Publication date: December 29, 2022Inventors: Gulbagh Singh, Chen-Hao Li, Chih-Ming Lee, Chi-Yen Lin, Cheng-Tsu Liu
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Publication number: 20220384455Abstract: An IC structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. From a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. First one of the long sides has a first stepped top-view profile. Second one of the long sides has a second stepped top-view profile. The first stepped top-view profile has more step rises than the second stepped top-view profile.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gulbagh SINGH, Shun-Chi TSAI, Chih-Ming LEE, Chi-Yen LIN, Kuo-Hung LO
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Publication number: 20220340754Abstract: A polyimide precursor includes a repeating unit of formulae (I) and (II): where R1 and R3 are each a tetravalent group of a tetracarboxylic dianhydride residue, and R2 and R4 are respectively a divalent group of a residue of a first-type diamine and a divalent group of a residue of a second-type diamine. The first-type diamine is represented by formula (III), and the second-type diamine is represented by formula (IV). A resin composition including the polyimide precursor, a polyimide formed from the polyimide precursor, and use of the polyimide are also disclosed.Type: ApplicationFiled: April 14, 2022Publication date: October 27, 2022Inventors: Kuan-Liang YEH, Chi-Yen LIN
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Patent number: 11462550Abstract: An SRAM structure includes first and second gate strips extending along a first direction. A first active region extends across the first gate strip from a top view, and forms a first pull-up transistor with the first gate strip. A second active region extends across the second gate strip from the top view, and forms a second pull-up transistor with the second gate strip. From the top view the first active region has a first stepped sidewall facing away from the second active region. The first stepped sidewall has a first side surface farthest from the second active region, a second side surface set back from the first side surface along the first direction, and a third side surface set back from the second side surface along the first direction.Type: GrantFiled: August 17, 2020Date of Patent: October 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gulbagh Singh, Shun-Chi Tsai, Chih-Ming Lee, Chi-Yen Lin, Kuo-Hung Lo
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Publication number: 20220208704Abstract: A semiconductor structure includes a first contact pad over an interconnect structure. The semiconductor structure further includes a second contact pad over the interconnect structure, wherein the second contact pad is electrically separated from the first contact pad. The semiconductor structure further includes a first buffer layer over the first contact pad, wherein the first buffer layer is partially over the second contact pad, and an edge of the second contact pad farthest from the first contact pad extends beyond the first buffer layer.Type: ApplicationFiled: March 18, 2022Publication date: June 30, 2022Inventors: Gulbagh SINGH, Chih-Ming LEE, Chi-Yen LIN, Wen-Chang KUO, C. C. LIU
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Method of designing a layout, method of making a semiconductor structure and semiconductor structure
Patent number: 11309268Abstract: A method of designing a layout includes determining a first layout pattern, wherein the first layout pattern corresponds to a plurality of contact pads. The method further includes generating a second layout pattern. The method further includes checking whether an edge of the second layout pattern overlaps the first layout pattern. The method further includes adjusting the second layout pattern so that the edge of the second layout pattern overlaps the first layout pattern in response to a determination that the edge of the second layout pattern is separated from the first layout pattern.Type: GrantFiled: June 17, 2020Date of Patent: April 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Gulbagh Singh, Chih-Ming Lee, Chi-Yen Lin, Wen-Chang Kuo, C. C. Liu -
Publication number: 20210384301Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor strip structure over a semiconductor substrate. The semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, and the spacing region is an undoped region. The method includes performing an implantation process over the first doped region and the spacing region to convert a first upper portion of the first doped region and a second upper portion of the spacing region into a continuous disorder region. The method includes forming a metal-semiconductor compound layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region after the implantation process.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gulbagh SINGH, Cheng-Yeh HUANG, Chin-Nan CHANG, Chih-Ming LEE, Chi-Yen LIN
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Patent number: 11101354Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region and extends over the isolation structure, the semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, the first doped region extends across the first active region, the spacing region is over the isolation structure, and the spacing region is an undoped region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region.Type: GrantFiled: August 3, 2020Date of Patent: August 24, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh Singh, Cheng-Yeh Huang, Chin-Nan Chang, Chih-Ming Lee, Chi-Yen Lin
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Publication number: 20210221032Abstract: A laser-debondable composition includes an acrylic resin, a light-shielding material, an additive, and a solvent. Wherein, the acrylic resin includes at least one nitrogen-containing organic group selected from a group consisting of tertiary amino groups and secondary amino groups, an organic group having a cyclic ether group, and an organic group having a hydroxyl group, and the additive includes at least one adhesion promoter. The laser-debondable composition has excellent adhesion ability to a substrate, attachability, and solvent resistance.Type: ApplicationFiled: January 20, 2021Publication date: July 22, 2021Inventors: Shih-Yun CHIU, Cheng-Wei LEE, Chi-Yen LIN
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Publication number: 20210040365Abstract: A temporary bonding composition is provided. The temporary bonding composition includes a polyfunctional crosslinker, a polymer and a solvent. The polyfunctional crosslinker includes a compound containing at least two functional groups selected from the group of blocked isocyanate groups, alkenyl ether groups, and alkoxyhydrocarbyl groups. Each of the blocked isocyanate groups is an isocyanate group protected by a blocking agent. The polymer has a functional group reacting to the polyfunctional crosslinker.Type: ApplicationFiled: December 29, 2019Publication date: February 11, 2021Inventors: Cheng-Wei LEE, Pei-Ci CHO, Chun-Hung HUANG, Min-Chi YANG, Chi-Yen LIN, Yuan-Li LIAO
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Publication number: 20200381441Abstract: An SRAM structure includes first and second gate strips extending along a first direction. A first active region extends across the first gate strip from a top view, and forms a first pull-up transistor with the first gate strip. A second active region extends across the second gate strip from the top view, and forms a second pull-up transistor with the second gate strip. From the top view the first active region has a first stepped sidewall facing away from the second active region. The first stepped sidewall has a first side surface farthest from the second active region, a second side surface set back from the first side surface along the first direction, and a third side surface set back from the second side surface along the first direction.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gulbagh SINGH, Shun-Chi TSAI, Chih-Ming LEE, Chi-Yen LIN, Kuo-Hung LO
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Publication number: 20200365696Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region and extends over the isolation structure, the semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, the first doped region extends across the first active region, the spacing region is over the isolation structure, and the spacing region is an undoped region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region.Type: ApplicationFiled: August 3, 2020Publication date: November 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh SINGH, Cheng-Yeh HUANG, Chin-Nan CHANG, Chih-Ming LEE, Chi-Yen LIN