Patents by Inventor Chi-Yi Chao

Chi-Yi Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11941338
    Abstract: Integrated circuits (IC) are provided. An IC includes a plurality of macros and a top channel. Each macro includes a macro boundary and a main pattern surrounded by the macro boundary. The top channel includes a plurality of first and second sub-channels. Each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. Each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. The macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. A first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yi Hu, Chih-Ming Chao, Chi-Yeh Yu
  • Patent number: 11915937
    Abstract: A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive material.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Mao-Lin Huang, Lung-Kun Chu, Huang-Lin Chao, Chi On Chui
  • Patent number: 11605886
    Abstract: An antenna assembly is provided having passive cooling elements that enable compact design. In one example, an antenna assembly is provided that includes a heat sink assembly having an interior side and an exterior side, an antenna array, an antenna circuit board, and a radome. The antenna circuit board includes at least one integrated circuit (IC) die. The IC die has a conductive primary heat dissipation path to the interior side of the heat sink assembly. The radome is coupled to the heat sink assembly and encloses the antenna circuit board and the antenna array between the radome and the heat sink assembly. The heat sink assembly includes a metal base plate and at least a first heat pipe embedded with the metal base plate. The first heat pipe is disposed between the metal base plate and the IC die.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: March 14, 2023
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Chi-Yi Chao, Lik Tsang, Jens Weis, Brendan Farley, Anthony Torza, Suresh Ramalingam
  • Patent number: 11373929
    Abstract: A cooling plate assembly and electronic device having the same are provided which utilize active and passive cooling devices for improved thermal management of one or more chip package assemblies included in the electronic device. In one example, a cooling plate assembly is provided that includes a cooling plate having a first surface and an opposing second surface, a first active cooling device coupled to the first surface of the cooling plate, and a first passive cooling device coupled to the second surface of the cooling plate.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: June 28, 2022
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Chi-Yi Chao, Suresh Ramalingam, Hoa Lap Do, Anthony Torza, Brian Philofsky, Arun Kumar Varadarajan Rajagopal
  • Patent number: 11330738
    Abstract: An electronic device is provided that balances the force applied to temperature control elements such that stress within components of the electronic device can be effectively managed. In one example, an electronic device is provided that includes a printed circuit board (PCB), a chip package, a thermal management system, a thermal spreader, and first and second biasing members. The chip package is mounted to the PCB. The thermal management system and spreader are disposed the opposite of the chip package relative to the PCB. The first biasing member is configured to control a first force sandwiching the chip package between the thermal spreader and the PCB. The second biasing member is configured to control a second force applied by the thermal management system against the thermal spreader. The first force can be adjusted separately from the second force so that total forces applied to the chip package and PCB may be effectively balanced.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: May 10, 2022
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Chi-Yi Chao, Huayan Wang, Suresh Ramalingam, Volker Aue
  • Patent number: 11328976
    Abstract: Some examples described herein provide for three-dimensional (3D) thermal management apparatuses for thermal energy dissipation of thermal energy generated by an electronic device. In an example, an apparatus includes a thermal management apparatus that includes a primary base, a passive two-phase flow thermal carrier, and fins. The thermal carrier has a carrier base and one or more sidewalls extending from the carrier base. The carrier base and the one or more sidewalls are a single integral piece. The primary base is attached to the thermal carrier. The carrier base has an exterior surface that at least a portion of which defines a die contact region. The thermal carrier has an internal volume aligned with the die contact region. A fluid is disposed in the internal volume. The fins are attached to and extend from the one or more sidewalls of the thermal carrier.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: May 10, 2022
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Chi-Yi Chao, Suresh Ramalingam, Hoa Lap Do, Anthony Torza, Brian D. Philofsky