Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: A method of fabricating a chip package is provided, and a chip package fabricated using the same are provided. The method includes connecting a photonic die to a substrate of the chip package and attaching a protection apparatus to the substrate. The method also includes attaching a photonic connector to the photonic die. At least a portion of the photonic connector is disposed inside a housing of the protection apparatus. A fabrication process is performed on the chip package while the photonic connector is inside the housing. After processing, the photonic connector is removed from the housing.

Abstract: An electronic device having a frame for coupling a plurality of thermal management devices to the printed circuit board is provided. The electronic device includes a first chip package mounted to the PCB and a second chip package mounted to the PCB. The frame is secured to the PCB, and the frame has a first aperture disposed over the first chip package and a second aperture disposed over the second chip package. The plurality of thermal management devices coupled to the frame includes a first thermal management device contacting an IC die of the first chip package through the first aperture and a second thermal management device contacting an IC die of the second chip package through the second aperture.

Abstract: A heat exchanger for a chip package is provided. The heat exchanger includes a body having an upper side, a lower side, and an internal cavity disposed in the body between the upper side and the lower side. A first outlet port and a second outlet port are formed in the body and are in fluid communication with the internal cavity. An inlet port is formed through the upper side of the body between the first and second outlet ports to supply fluid into the internal cavity.

Abstract: A chip package includes a substrate and an integrated circuit (“IC”) die mounted to the substrate. A stiffener frame is mounted to the substrate and circumscribes the IC die. The stiffener frame has a plurality of connected walls that define an opening in the stiffener frame. The chip package also includes a lid having a bottom side facing a top surface of the IC die. The lid has at least a first guide and a second guide extending from the bottom side of the lid. The first guide can be disposed outward or inward of the stiffener frame. The first guide has a side facing an outer wall surface or an inner wall surface of the stiffener frame. The first guide and the second guide are positioned to limit movement of the lid relative to the stiffener frame in two directions.

Abstract: An antenna assembly is provided having passive cooling elements that enable compact design. In one example, an antenna assembly is provided that includes a heat sink assembly having an interior side and an exterior side, an antenna array, an antenna circuit board, and a radome. The antenna circuit board includes at least one integrated circuit (IC) die. The IC die has a conductive primary heat dissipation path to the interior side of the heat sink assembly. The radome is coupled to the heat sink assembly and encloses the antenna circuit board and the antenna array between the radome and the heat sink assembly. The heat sink assembly includes a metal base plate and at least a first heat pipe embedded with the metal base plate. The first heat pipe is disposed between the metal base plate and the IC die.

Abstract: A cooling plate assembly and electronic device having the same are provided which utilize active and passive cooling devices for improved thermal management of one or more chip package assemblies included in the electronic device. In one example, a cooling plate assembly is provided that includes a cooling plate having a first surface and an opposing second surface, a first active cooling device coupled to the first surface of the cooling plate, and a first passive cooling device coupled to the second surface of the cooling plate.

Abstract: Some examples described herein provide for three-dimensional (3D) thermal management apparatuses for thermal energy dissipation of thermal energy generated by an electronic device. In an example, an apparatus includes a thermal management apparatus that includes a primary base, a passive two-phase flow thermal carrier, and fins. The thermal carrier has a carrier base and one or more sidewalls extending from the carrier base. The carrier base and the one or more sidewalls are a single integral piece. The primary base is attached to the thermal carrier. The carrier base has an exterior surface that at least a portion of which defines a die contact region. The thermal carrier has an internal volume aligned with the die contact region. A fluid is disposed in the internal volume. The fins are attached to and extend from the one or more sidewalls of the thermal carrier.

Abstract: An electronic device is provided that balances the force applied to temperature control elements such that stress within components of the electronic device can be effectively managed. In one example, an electronic device is provided that includes a printed circuit board (PCB), a chip package, a thermal management system, a thermal spreader, and first and second biasing members. The chip package is mounted to the PCB. The thermal management system and spreader are disposed the opposite of the chip package relative to the PCB. The first biasing member is configured to control a first force sandwiching the chip package between the thermal spreader and the PCB. The second biasing member is configured to control a second force applied by the thermal management system against the thermal spreader. The first force can be adjusted separately from the second force so that total forces applied to the chip package and PCB may be effectively balanced.