Abstract: A method for preventing redundant events from toggling the core logic during scan data shifting mode is provided. A logic element is controlled by SEL. During scan data shifting mode, no toggled data will interfere with the core logic because the logic element is shut off. Only the scan path (SI-SO-SI) continues toggling. Therefore, redundant events are prevented from toggling the core logic. Therefore the simulation time is reduced and the verification flow is sped up. Additionally, the power consumption during testing is significantly reduced.

Abstract: The invention provides an improvement in a cell structure for gate arrays. By using the cell in gate arrays, the design flexibility and the symmetry feature of the gate array can be retained. By providing transistors of different sizes, the design can possess more flexibility and more efficiency. Moreover, a denser chip layout can be completed. Thus, average wire lengths used for interconnections in the chip design may be shorter than previously possible. Also, better utilization of available chip area can be made. Thus, it becomes possible to flexibly and optimally use every area of the chip.