Abstract: The present disclosure relates to a low glycosylated spike protein and a vaccine designed to express the spike protein in vivo. The present disclosure also teaches a method for generating an immune response by utilizing the low glycosylated spike protein, which provides a broader protection across different variants. A method for identifying a glycan-shielded conserved peptide of a glycoprotein is also disclosed.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: Methods for revitalizing components of a plasma processing apparatus that includes a sensor for detecting a thickness or roughness of a peeling weakness layer on a protective surface coating of a plasma processing tool and/or for detecting airborne contaminants generated by such peeling weakness layer. The method includes detecting detrimental amounts of peeling weakness layer buildup or airborne concentration of atoms or molecules from the peeling weakness layer, and initiating a revitalization process that bead beats the peeling weakness layer to remove it from the component while maintaining the integrity of the protective surface coating.

Abstract: A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.

Abstract: Disclosed herein are novel single-stranded anti-sense oligonucleotides (ASOs) capable of reducing the transcription of thioredoxin domain containing protein 5 (TXNDC5) mRNA. Also disclosed is use of the single-stranded ASOs as disclosed herein for manufacturing medicaments suitable for treating a disease associated with upregulation of TXNDC5. Accordingly, a pharmaceutical composition comprising the disclosed ASO molecules is provided; as well as a method of treating a subject suffering from TXNDC5-mediated disease via administering to the subject the disclosed single-stranded ASO molecules.

Abstract: A purification device for exercise environment is provided and includes a main body, a purification unit, a gas guider and a gas detection module. The purification unit, the gas guider and the gas detection module are disposed in the main body to guide the gas outside the main body through the purification unit for filtering and purifying the gas, and discharge a purified gas. The gas detection module detects particle concentration of suspended particles contained in the purified gas. The gas guider is controlled to operate and export the gas at an airflow rate within 3 minutes. The particle concentration of the suspended particles contained in the purified gas, which is filtered by the purification unit, is reduced to and less than 0.75 ?g/m3. Consequently, the purified gas is filtered, and an exerciser in an exercise environment can breathe with safety.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.

Abstract: A method includes forming a first semiconductor channel region and a second semiconductor channel region, with the second semiconductor channel region overlapping the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A dipole dopant is incorporated into a first one of the first gate dielectric and the second gate dielectric to a higher atomic percentage, and a second one of the first gate dielectric and the second gate dielectric has a lower atomic percentage of the dipole dopant. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric. The gate electrode and the first gate dielectric form parts of a first transistor, and the gate electrode and the second gate dielectric form parts of a second transistor.

Abstract: A package structure includes a leadframe, at least two dies, at least one spacer and a plastic package material. The leadframe includes a die pad. The dies are disposed on the die pad of the leadframe. The spacer is disposed between at least one of the dies and the die pad. The plastic package material is disposed on the leadframe, and covers the dies. A first minimum spacing distance is between one of a plurality of edges of the spacer and one of a plurality of edges of the die pad, a second minimum spacing distance is between one of a plurality of edges of the dies and one of the edges of the die pad, and the first minimum spacing distance is larger than the second minimum spacing distance.

Abstract: A package structure includes a leadframe, a semiconductor die and a plastic package material. The leadframe includes a die pad and a plurality of leads. The leads are disposed on four peripheral regions of the die pad, and each of the leads includes a main body, at least one extending portion and a plurality of plating surfaces. The extending portion is connected to the main body, and the main body and the extending portion are integrally formed. The plating surfaces are disposed on the main body and the extending portion. The semiconductor die is disposed on the die pad of the leadframe. The plastic package material is disposed on the leadframe. The main body and the extending portion of each of the leads protrude a peripheral region of the plastic package material.

Abstract: A package structure includes a leadframe, a semiconductor die and a plastic package material. The leadframe includes a die pad and a plurality of leads. The leads are disposed on four sides of the die pad, and each of the leads includes a plurality of plating surfaces. The semiconductor die is disposed on the die pad of the leadframe. The plastic package material is disposed on the leadframe. Each of the leads protrudes an outer region of the plastic package material.