Patents by Inventor Chi-Ying CHEN

Chi-Ying CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240159269
    Abstract: A rotary bearing assembly is disclosed and includes an input shaft, an inner-ring component, an outer-ring component and a load element. The input shaft is configured to combine a rotating shaft of a motor to provide a power input. The inner-ring component includes a gear set, wherein the inner-ring component is sleeved on the input shaft through the gear set and driven by the input shaft. The outer-ring component is sleeved on the inner-ring component through a load element and engaged with the gear set, wherein when the gear set is driven by the input shaft to drive the inner-ring component, the gear set drives the outer-ring component, and the inner-ring component and the outer-ring component are rotated relatively, wherein one of the inner-ring component and the outer-ring component is served to provide a power output, and a rotational speed difference is between the power input and the power output.
    Type: Application
    Filed: August 8, 2023
    Publication date: May 16, 2024
    Inventors: Chi-Wen Chung, Hung-Wei Lin, Hsien-Lung Tsai, Wei-Ying Chu, Chin-Hsiang Chen
  • Patent number: 11964881
    Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 23, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
  • Publication number: 20240128375
    Abstract: A method includes forming first and second semiconductor fins and a gate structure over a substrate; forming a first and second source/drain epitaxy structures over the first and second semiconductor fins; forming an interlayer dielectric (ILD) layer over the first and second source/drain epitaxy structures; etching the gate structure and the ILD layer to form a trench; performing a first surface treatment to modify surfaces of a top portion and a bottom portion of the trench to NH-terminated; performing a second surface treatment to modify the surfaces of the top portion of the trench to N-terminated, while leaving the surfaces of the bottom portion of the trench being NH-terminated; and depositing a first dielectric layer in the trench, wherein the first dielectric layer has a higher deposition rate on the surfaces of the bottom portion of the trench than on the surfaces of the bottom portion of the trench.
    Type: Application
    Filed: March 16, 2023
    Publication date: April 18, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Yi CHANG, Yu Ying CHEN, Zhen-Cheng WU, Chi On CHUI
  • Publication number: 20240088224
    Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: HSING-I TSAI, FU-HUAN TSAI, CHIA-CHUNG CHEN, HSIAO-CHUN LEE, CHI-FENG HUANG, CHO-YING LU, VICTOR CHIANG LIANG
  • Publication number: 20240071767
    Abstract: A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.
    Type: Application
    Filed: January 6, 2023
    Publication date: February 29, 2024
    Inventors: Hsueh-Ju Chen, Chi On Chui, Tsung-Da Lin, Pei Ying Lai, Chia-Wei Hsu
  • Publication number: 20230220026
    Abstract: The current invention provides the nucleic acid carrier for producing the single-chain VEGF fusion protein comprising the same, and methods of making and using the same.
    Type: Application
    Filed: January 12, 2022
    Publication date: July 13, 2023
    Inventors: Ching-Wei LUO, Chi-Ying CHEN