Patents by Inventor Chi-Ying WU

Chi-Ying WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12266543
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The semiconductor device structure includes a metal gate stack over the isolation layer and wrapping around an upper part of the fin portion. The metal gate stack includes a gate dielectric layer and a metal gate electrode layer over the gate dielectric layer, and the gate dielectric layer includes fluorine. A first part of the isolation layer is not covered by the metal gate stack, the first part includes fluorine, and a first concentration of fluorine in the first part increases toward a first top surface of the first part.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Ming Chang, Chih-Cheng Lin, Chi-Ying Wu, Wei-Ming You, Ziwei Fang, Huang-Lin Chao
  • Publication number: 20240395564
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The isolation layer includes fluorine, and a first concentration of fluorine in the isolation layer increases toward a top surface of the isolation layer. The semiconductor device structure includes a gate stack over the isolation layer and wrapping around the fin portion.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Ming CHANG, Chih-Cheng LIN, Chi-Ying WU, Wei-Ming YOU, Ziwei FANG, Huang-Lin CHAO
  • Publication number: 20240290588
    Abstract: An ion collector includes a plurality of segments and a plurality of integrators. The plurality of segments are physically separated from one another and spaced around a substrate support. Each of the segments includes a conductive element that is designed to conduct a current based on ions received from a plasma. Each of the plurality of integrators is coupled to a corresponding conductive element. Each of the plurality of integrators is designed to determine an ion distribution for a corresponding conductive element based, at least in part, on the current conducted at the corresponding conductive element. An example benefit of this embodiment includes the ability to determine how uniform the ion distribution is across a wafer being processed by the plasma.
    Type: Application
    Filed: May 3, 2024
    Publication date: August 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Otto CHEN, Chi-Ying WU, Chia-Chih CHEN
  • Patent number: 11996276
    Abstract: An ion collector includes a plurality of segments and a plurality of integrators. The plurality of segments are physically separated from one another and spaced around a substrate support. Each of the segments includes a conductive element that is designed to conduct a current based on ions received from a plasma. Each of the plurality of integrators is coupled to a corresponding conductive element. Each of the plurality of integrators is designed to determine an ion distribution for a corresponding conductive element based, at least in part, on the current conducted at the corresponding conductive element. An example benefit of this embodiment includes the ability to determine how uniform the ion distribution is across a wafer being processed by the plasma.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Otto Chen, Chi-Ying Wu, Chia-Chih Chen
  • Publication number: 20230197424
    Abstract: An ion collector includes a plurality of segments and a plurality of integrators. The plurality of segments are physically separated from one another and spaced around a substrate support. Each of the segments includes a conductive element that is designed to conduct a current based on ions received from a plasma. Each of the plurality of integrators is coupled to a corresponding conductive element. Each of the plurality of integrators is designed to determine an ion distribution for a corresponding conductive element based, at least in part, on the current conducted at the corresponding conductive element. An example benefit of this embodiment includes the ability to determine how uniform the ion distribution is across a wafer being processed by the plasma.
    Type: Application
    Filed: February 13, 2023
    Publication date: June 22, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Otto CHEN, Chi-Ying WU, Chia-Chih CHEN
  • Patent number: 11581169
    Abstract: An ion collector includes a plurality of segments and a plurality of integrators. The plurality of segments are physically separated from one another and spaced around a substrate support. Each of the segments includes a conductive element that is designed to conduct a current based on ions received from a plasma. Each of the plurality of integrators is coupled to a corresponding conductive element. Each of the plurality of integrators is designed to determine an ion distribution for a corresponding conductive element based, at least in part, on the current conducted at the corresponding conductive element. An example benefit of this embodiment includes the ability to determine how uniform the ion distribution is across a wafer being processed by the plasma.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Otto Chen, Chi-Ying Wu, Chia-Chih Chen
  • Publication number: 20210280432
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The semiconductor device structure includes a metal gate stack over the isolation layer and wrapping around an upper part of the fin portion. The metal gate stack includes a gate dielectric layer and a metal gate electrode layer over the gate dielectric layer, and the gate dielectric layer includes fluorine. A first part of the isolation layer is not covered by the metal gate stack, the first part includes fluorine, and a first concentration of fluorine in the first part increases toward a first top surface of the first part.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Ming CHANG, Chih-Cheng LIN, Chi-Ying WU, Wei-Ming YOU, Ziwei FANG, Huang-Lin CHAO
  • Patent number: 11018022
    Abstract: A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Ming Chang, Chih-Cheng Lin, Chi-Ying Wu, Wei-Ming You, Ziwei Fang, Huang-Lin Chao
  • Publication number: 20200111651
    Abstract: An ion collector includes a plurality of segments and a plurality of integrators. The plurality of segments are physically separated from one another and spaced around a substrate support. Each of the segments includes a conductive element that is designed to conduct a current based on ions received from a plasma. Each of the plurality of integrators is coupled to a corresponding conductive element. Each of the plurality of integrators is designed to determine an ion distribution for a corresponding conductive element based, at least in part, on the current conducted at the corresponding conductive element. An example benefit of this embodiment includes the ability to determine how uniform the ion distribution is across a wafer being processed by the plasma.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Otto Chen, Chi-Ying Wu, Chia-Chih Chen
  • Patent number: 10553411
    Abstract: An ion collector includes a plurality of segments and a plurality of integrators. The plurality of segments are physically separated from one another and spaced around a substrate support. Each of the segments includes a conductive element that is designed to conduct a current based on ions received from a plasma. Each of the plurality of integrators is coupled to a corresponding conductive element. Each of the plurality of integrators is designed to determine an ion distribution for a corresponding conductive element based, at least in part, on the current conducted at the corresponding conductive element. An example benefit of this embodiment includes the ability to determine how uniform the ion distribution is across a wafer being processed by the plasma.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: February 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Otto Chen, Chi-Ying Wu, Chiah-Chih Chen
  • Publication number: 20200020544
    Abstract: A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Ming CHANG, Chih-Cheng LIN, Chi-Ying WU, Wei-Ming YOU, Ziwei FANG, Huang-Lin CHAO