Abstract: A charge-discharge method applied to an electronic device for controlling a charging and a discharging of a vehicle, the electronic device communicates with a charging pile. The charge-discharge method comprises collecting operation behavior information of a user with respect to household appliances, inputting the operation behavior information into a preset travel time prediction model to obtain a first driving travel time of the user, determining a first charge-discharge strategy of the vehicle of the user based on the first driving travel time, and transmitting the first charge-discharge strategy to the charging pile. The charging pile charges the vehicle or controls the vehicle to discharge based on the first charge-discharge strategy. An electronic device and a non-transitory storage are also disclosed.

Abstract: A method for calibrating a data reception window includes: (A) setting a level of a reference voltage by different predetermined values and repeatedly sampling a data signal to obtain multiple first valid data reception windows; (B) establishing a first eye diagram based on the first valid data reception windows; (C) resetting the level of the reference voltage by the predetermined values combined with a first offset and repeatedly sampling the data signal according to the reference voltage to obtain multiple second valid data reception windows and (D) selectively updating the first eye diagram according to the second valid data reception windows. When width of a second valid data reception window is greater than width of a first valid data reception window corresponding to the same predetermined value, the first valid data reception window in the first eye diagram is replaced by the second valid data reception window.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to implement seamless switching of dynamic range and/or refresh rate on display devices. An example apparatus disclosed herein causes a display to activate panel self refresh after a command to switch a graphics output from a first dynamic range to a second dynamic range, the graphics output provided to the display. The example apparatus also switches the graphics output from the first dynamic range to the second dynamic range after the panel self refresh is activated. The example apparatus further causes the display to deactivate the panel self refresh after the graphics output is switched to the second dynamic range.

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions arranged on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

Abstract: Semiconductor devices are provided. A semiconductor device includes a power switch, a first power mesh and a second power mesh. The power switch has a first terminal and a second terminal. The first power mesh is directly connected to the first terminal of the power switch. The second power mesh is directly connected to the second terminal of the power switch. The first power mesh includes a first power rail over the power switch and extending in a first direction. The second power mesh includes a second power rail under the power switch and extending in the first direction. The first and second power rails are separated from each other.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.

Abstract: Disclosed is a display substrate including a base substrate, which includes first and second display regions, and at least one first data line. The first display region includes first and second sub-display regions located on opposite sides of the second display region along a first direction and a third sub-display region located on at least one side of the second display region along a second direction. The first data line includes a first sub-data line located in the first sub-display region and connected with a pixel circuit of the first sub-display region, a second sub-data line located in the second sub-display region and connected with a pixel circuit of the second sub-display region, and a third sub-data line which is connected with the first and second sub-data lines, located in the third sub-display region, and connected with at least one second pixel circuit of the third sub-display region.

Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.

Abstract: A signal transporting system, comprising: a signal transporting circuit, configured to receive an input signal to generate an output signal; and a signal timing adjusting circuit, configured to adjust an output timing of the output signal according to a signal pattern of the input signal.

Abstract: A display panel and a display device are provided. In the display panel, a first display region includes first light-emitting units, and a second display region includes second light-emitting units, first pixel circuits and second pixel circuits, the first pixel circuit is connected with the first light-emitting unit, and the second pixel circuit is connected with the second light-emitting unit. The first display region includes a first region and a second region on a side of the first region away from the second display region, the second display region includes a third region and a fourth region on a side of the third region close to the first display region, the first light-emitting unit in the first region is connected with the first pixel circuit in the third region, the first light-emitting unit in the second region is connected with the first pixel circuit in the fourth region.

Abstract: A display substrate and a display device are provided. The display substrate includes a display region, at least one first signal line, and at least one connecting wire. The display region includes a first display region and a second display region; the first display region includes at least one first light emitting element, and the second display region includes at least one first pixel circuit; the first signal line includes a first main body portion and a first winding portion; the first main body portion extends along a first direction, and at least part of the first winding portion extends along a direction intersecting with the first direction; at least one first signal line is electrically connected to at least one first pixel circuit; and at least one first pixel circuit is configured to respectively drive at least one first light emitting element.

Abstract: A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.

Abstract: A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Abstract: A device includes a plurality of tracks, wherein at least one of the plurality of tracks comprises a first power rail for a first voltage. The device further includes a first via in electrical contact with the power rail. The device further includes a first contact in electrical contact with the first via. The device further includes a first transistor in electrical contact with the first contact. The device further includes a second transistor in electrical isolation with the first transistor. The device further includes a second contact in electrical contact with the second transistor. The device further includes a second via in electrical contact with the second contact. The device further includes a second power rail in electrical contact with the second via, wherein the second power rail is configured to carry a second voltage.

Abstract: A display substrate and a display device are provided. The display substrate includes a display region, at least one first signal line, and at least one connecting wire. The display region includes a first display region and a second display region; the first display region includes at least one first light emitting element, and the second display region includes at least one first pixel circuit; the first signal line includes a first main body portion and a first winding portion; the first main body portion extends along a first direction, and at least part of the first winding portion extends along a direction intersecting with the first direction; at least one first signal line is electrically connected to at least one first pixel circuit; and at least one first pixel circuit is configured to respectively drive at least one first light emitting element.

Abstract: Provided is a display panel, including a base substrate provided with a first display region and a second display region and a plurality of pixels and a packaging layer that are sequentially arranged on the base substrate. The packaging layer includes a first organic layer, and the second display region has a relatively large transmittance. The second display region includes a first sub-display region and a second sub-display region that is proximal to a border of the base substrate relative to the first sub-display region. A difference between a maximum thickness and a minimum thickness of a first portion, disposed in the second display region, of the first organic layer is less than a difference between a maximum thickness and a minimum thickness of a second portion disposed in the second sub-display region.

Abstract: A panel driving device includes a processor. In a first frame, an initial scan signal has an initial scan pulse signal. In a second frame, the initial scan signal has the initial scan pulse signal, and the second frame is located after the first frame. In the second frame, the processor shifts an initial light emitting pulse signal of an initial light emitting signal by the first period and an offset period, and a pulse period of the initial light emitting pulse signal does not overlap a pulse period of the initial scan pulse signal, and the offset period is associated with a frame number.

Abstract: The present disclosure discloses a memory signal calibration apparatus and a memory signal calibration method. A gating circuit generates a data strobe enablement setting signal according to a setting control signal, generates an enabling state of the data strobe enablement signal and performs gating on a data strobe signal according to the enabling state to generate a gated data strobe signal.