Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions arranged on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

Abstract: Semiconductor devices are provided. A semiconductor device includes a power switch, a first power mesh and a second power mesh. The power switch has a first terminal and a second terminal. The first power mesh is directly connected to the first terminal of the power switch. The second power mesh is directly connected to the second terminal of the power switch. The first power mesh includes a first power rail over the power switch and extending in a first direction. The second power mesh includes a second power rail under the power switch and extending in the first direction. The first and second power rails are separated from each other.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.

Abstract: A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Abstract: A device includes a plurality of tracks, wherein at least one of the plurality of tracks comprises a first power rail for a first voltage. The device further includes a first via in electrical contact with the power rail. The device further includes a first contact in electrical contact with the first via. The device further includes a first transistor in electrical contact with the first contact. The device further includes a second transistor in electrical isolation with the first transistor. The device further includes a second contact in electrical contact with the second transistor. The device further includes a second via in electrical contact with the second contact. The device further includes a second power rail in electrical contact with the second via, wherein the second power rail is configured to carry a second voltage.

Abstract: A method of forming a semiconductor device includes forming first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction, and correspondingly overlap and electrically couple to a doped region. The method further includes forming a via-to-via (V2V) rail which extends in a second direction angled with respect to the first direction, wherein the V2V rail overlaps at least of the first MD contact structure or the third MD contact structure. The method further includes forming a first via-to-MD (VD) structure over, and electrically coupled to, the first MD contact structure and the V2V rail. The method further includes forming a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and is electrically coupled to the first VD structure.

Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: A device including a first vertical field effect transistor having a first drain/source region and a second drain/source region, and a second vertical field effect transistor having a third drain/source region and a fourth drain/source region. The device including a first power contact situated on a frontside of the device and coupled to the first drain/source region, a second power contact situated on the frontside of the device and coupled to the third drain/source region, and a contact situated on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region.

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

Abstract: An integrated circuit includes a first-type active-region structure and a second-type active-region structure extending in a first direction and a first terminal-conductor and a second terminal-conductor extending in a second direction. The integrated circuit also includes a first power stub and a second power stub in a first metal layer and a first power line and a second power line in a second metal layer. The integrated circuit further includes a first via connector directly connected between the first power stub and the first terminal-conductor, a second via connector directly connected between the second power stub and the second terminal-conductor, a third via connector directly connected between the first power stub and the first power line, and a fourth via connector directly connected between the second power stub and the second power line.

Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate, a power switch, a first power mesh and a second power mesh. The power switch is formed over the front surface of the semiconductor substrate. The first power mesh is formed over the power switch and is directly connected to the first terminal of the power switch. The second power mesh is formed over the back surface of the semiconductor substrate and is directly connected to the second terminal of the power switch.

Abstract: A detection method of polyamines is used to solve the problem that the conventional method is not suitable for detecting polyamines. The detection method of polyamines includes providing a sample with polyamines. The sample and a derivatization reagent with an isothiocyanate group are dissolved in a working solution to form a mixture, while a thiocarbamoylation reaction between the polyamine in the sample and the derivatization reagent is performed to obtain a derivatization solution with a thiourea derivative. The thiourea derivative in the derivatization solution is then detected to obtain a value of polyamine. With such performance, polyamine in the sample can be effectively detected. A diagnostic method of cancers is also disclosed.

Abstract: A semiconductor device (having a VFET architecture) includes: first and second active regions (ARs); first and second metal-to-gate (MG) contacts proximal to channel regions of the first and second ARs; metal-to-source/drain (MD) contacts and buried MD (BMD) contacts correspondingly coupled to first and second S/D regions correspondingly of the first and second ARs; and a metal-to-gate (MP) contact at a same level as the MG contacts, and extending between and coupling together the first and second MG contacts; and relative to a first direction, the first and second ARs being substantially aligned; and at least a portion of the MP contact extending substantially beyond each of the first and second ARs relative to a perpendicular second direction.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: A method of making a semiconductor device includes forming a first device on a first side of a substrate, wherein the first device comprises a first source/drain (S/D) electrode. The method further includes forming a second device on a second side of the substrate, wherein the second side of the substrate is opposite the first side of the substrate, and the second device comprises a second S/D electrode. The method further includes forming a through substrate via (TSV) electrically connecting the first S/D electrode to the second S/D electrode, wherein a width of the TSV is equal to a width of at least one of the first S/D electrode or the second S/D electrode.

Abstract: An integrated circuit (IC) structure includes a first transistor including a first gate structure adjacent to first and second portions of a first active area positioned in a semiconductor substrate, a second transistor including a second gate structure adjacent to the second portion of the first active area and a third portion of the first active area, an isolation structure overlying the second portion of the first active area, and first through third metal-like defined (MD) segments overlying the respective first through third portions of the first active area. The first and third MD segments are electrically connected to the respective first and third portions of the first active area, and the second MD segment is electrically isolated from the second portion of the first active area by the isolation structure.

Abstract: A semiconductor structure includes a first upper source/drain region, a second upper source/drain region, a first lower source/drain contact, a second lower source/drain contact, and a third conductive region. The first upper source/drain contact is disposed at a first elevation. The second upper source/drain contact is disposed at the first elevation. The first lower source/drain contact is disposed at a second elevation. The second lower source/drain contact is disposed at the second elevation. The third conductive region is disposed at a third elevation. A projection area of the third conductive region is disposed between a projection area of the first upper source/drain contact and a projection area of the second upper source/drain contact. The third elevation is disposed between the first elevation and the second elevation.

Abstract: An integrated circuit structure includes a first and second power rail on a first level, a first and second set of conductive structures on a second level and a first, second and third conductive structure on a third level. The first set of conductive structures is over the first power rail. The second set of conductive structures is over the second power rail. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and a first conductive structure of the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and a second conductive structure of the second set of conductive structures. The third conductive structure overlaps a third conductive structure of the first set of conductive structures and a third conductive structure of the second set of conductive structures.