Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a conductive mesh on a first side of the substrate. The semiconductor device further includes an active region on a second side of the substrate, wherein the first side of the substrate is opposite to the second side of the substrate. The semiconductor device further includes a through via electrically connected to the conductive mesh, wherein the through via extends through the substrate. The semiconductor device further includes a contact structure on the second side of the substrate, wherein the contact structure is electrically connected to the active region, the contact structure is in direct contact with the through via, and the contact structure overlaps a top surface of the through via in a top view.

Abstract: A semiconductor structure includes a first upper source/drain region, a second upper source/drain region, a first lower source/drain contact, a second lower source/drain contact, and a third conductive region. The first upper source/drain contact is disposed at a first elevation. The second upper source/drain contact is disposed at the first elevation. The first lower source/drain contact is disposed at a second elevation. The second lower source/drain contact is disposed at the second elevation. The third conductive region is disposed at a third elevation. A projection area of the third conductive region is disposed between a projection area of the first upper source/drain contact and a projection area of the second upper source/drain contact. The third elevation is disposed between the first elevation and the second elevation.

Abstract: A semiconductor structure includes a top transistor device stacked on a bottom transistor device. The semiconductor structure further includes a via in direct contact with a top electrode of the top transistor device and a bottom electrode of the bottom transistor device. The semiconductor structure further includes a top contact directly contacting the top electrode of the top transistor device.

Abstract: An integrated circuit device includes first and second stack structures and a side connection structure. The first stack structure includes a first transistor and a second transistor stacked thereon. The second stack structure includes a third transistor and a fourth transistor stacked thereon. Each of the first to fourth transistors includes an active layer having a channel region and a source/drain region, a gate structure wrapping around the channel region, and a source/drain contact surrounding the source/drain region. The active layer and the side connection structure extend substantially along a first direction in a top view, and the gate structure extends substantially along a second direction orthogonal to the first direction in the top view. The side connection structure electrically connects one of the source/drain contact and the gate structure of the first transistor to one of the source/drain contact and the gate structure of the third transistor.

Abstract: A stereoscopic arch ignitor resistor and manufacturing method thereof are provided. The stereoscopic arch ignitor resistor includes a substrate, an alloy layer, a combustible material accommodating portion, and a lateral conductive layer. The alloy layer is disposed on a first surface of the substrate. The alloy layer includes an arch lead, a first connecting portion, and a second connecting portion. The combustible material accommodating portion is positioned between the arched lead and the substrate. The arch lead defines a volume of combustible material of the combustible material accommodating portion. The lateral conductive layer is disposed on the alloy layer. The lateral conductive layer abuts against a side surface of the substrate. The stereoscopic arch-type ignition resistance element is configured to reduce ignition distance and/or increase contact area with combustible material.

Abstract: An integrated circuit includes a first-type active-region structure and a second-type active-region structure extending in a first direction and a first terminal-conductor and a second terminal-conductor extending in a second direction. The integrated circuit also includes a first power stub and a second power stub in a first metal layer and a first power line and a second power line in a second metal layer. The integrated circuit further includes a first via connector directly connected between the first power stub and the first terminal-conductor, a second via connector directly connected between the second power stub and the second terminal-conductor, a third via connector directly connected between the first power stub and the first power line, and a fourth via connector directly connected between the second power stub and the second power line.

Abstract: Provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure extending and a second-type active-region semiconductor structure both extending in a first direction. The second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device still includes a front-side power rail extending in the second direction in the front-side conductive layer and a back-side power rail extending in the second direction in the back-side conductive layer. The integrated circuit device further includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.

Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.

Abstract: A flattening resistor and a manufacturing method thereof are provided. The flattening resistor includes a substrate, a resistive layer, and an electrode layer. The present disclosure solves the problems of increased impedance and abnormal product characteristics caused by improper jointing of the interface between the electrode layer and the resistive layer, which includes using laser-cutting or grinding to eliminate the step difference of the interface and process the discontinuous structure of the electrode layer after the electrode layer process is completed.

Abstract: A columnar resistor and a method of laser trimming for manufacturing the same are provided. The columnar resistor includes a resistance layer disposed on the surface of a columnar substrate and the resistive layer includes a resistance determining area, a first resistance adjustment area, and a second resistance adjustment area. The resistance determining area is configured to form a first laser-trimming line and achieve a first resistance value by a first laser-trimming. The first resistance adjustment area is configured to form a second laser-trimming line and achieve a second resistance value by a second laser-trimming. The resistance value is precisely adjusted by two laser-trimming processes of the resistive layer, thereby improving the stability of product manufacturing.

Abstract: A method includes a first set of active areas extending in a first direction and separated from each other along a second direction in a cell; first and second gates that cross the first set of active areas along the second direction, the first gate being shared by a first transistor of a first type and a second transistor of a second type and the second gate being shared by a third transistor of the first type and a fourth transistor of the second type; and a set of conductive lines arranged in three metal tracks in the cell and coupling at least one of terminals of the first to fourth transistors to another one of the terminals of the first to fourth transistor. The first transistor is turned off to electrically disconnect a source/drain terminal of the first transistor from a source/drain terminal of the fourth transistor.

Abstract: A high-temperature resistant resistor is provided and includes a substrate layer, a first surface electrode layer, and a second surface electrode layer. The first surface electrode layer is disposed on a first surface of the substrate layer, the resistance layer partially attaches the first electrode layer and the substrate layer, the second surface electrode layer is aligned with the first surface electrode layer, and attached on the first surface electrode layer and the resistance layer, so that the resistance layer is fixed between the first electrode layer and the second electrode layer. The first surface electrode layer, the resistance layer and the second surface electrode layer form a composite structure to suppress the change in resistance value of the high-temperature resistant resistor at high temperatures.

Abstract: A method includes forming an epitaxial stack including a first sacrificial layer, a channel layer, and a second sacrificial layer over a semiconductor substrate; patterning the epitaxial stack into a fin structure such that opposite first ends of the channel layer are exposed; recessing the opposite first ends of the channel layer; forming first dummy spacers on the recessed opposite first ends of the channel layer; forming an isolation structure in the fin structure; recessing a top surface of the isolation structure to a position lower than a bottom surface of the channel layer, such that opposite second ends of the channel layer are exposed; recessing the opposite second ends of the channel layer; forming second dummy spacers on the recessed opposite second ends of the channel layer; and replacing the first dummy spacers and the second dummy spacers with a metal gate structure.

Abstract: A semiconductor structure includes a first transistor, a second transistor, a gate structure, and a gate isolation. The first transistor is of a first conductivity type and comprises a first active region structure. The second transistor is of a second conductivity type different from the first conductivity type and comprises a second active region structure. The second transistor is disposed above the first transistor. The gate structure comprises a first gate connection contacting the first active region structure and a second gate connection contacting the second active region structure. The gate isolation is disposed between the first gate connection and the second gate connection.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device has a cell. The cell includes a gate structure, a first active region, a second active region, a first signal line, and a second signal line. The gate structure extends along a first direction. The first active region extends along a second direction different from the first direction and intersects the gate structure. The second active region extends along the second direction and intersects the gate structure. The first active region overlaps the second active region along a third direction different from the first direction and the second direction. The first signal line is over the first active region and configured to transmit an input signal. The second signal line is under the second active region and configured to transmit an output signal.

Abstract: An integrated circuit including a first cell and a second cell. The first cell includes a first plurality of active areas that extend in a first direction and a first plurality of gates that extend in a second direction that crosses the first direction, the first cell having first cell edges defined by breaks in the first plurality of gates. The second cell includes a second plurality of active areas that extend in the first direction and a second plurality of gates that extend in the second direction, the second cell having second cell edges defined by breaks in the second plurality of gates. Each of the second plurality of active areas is larger than each of the first plurality of active areas and the first cell is adjacent the second cell such that the first cell edges align with the second cell edges.

Abstract: An electronic device including a first electronic element, a second electronic element, a first signal track, and a second signal track is provided. The second electronic element is different from the first electronic element. The first signal track is electrically connected to the first electronic element. The second signal track is electrically connected to the second electronic element and electrically separated from the first signal track. A width of the second signal track is substantially 8˜100 nm. The first signal track has a larger cross-sectional area than the second signal track.

Abstract: A cell region (of a device) includes: a first active region (AR); first MD structures aligning to beta tracks; and in a first metallization layer, segments aligning to alpha tracks. For one or more first or second locations, a corresponding region of the first AR is configurable as a source region or a drain region. For one or more third locations, a corresponding region of the first AR is configurable as a source region, but not as a drain region. For one or more fourth locations, a corresponding region of the AR is not configurable as a source region or a drain region. Each of the first to fourth locations is at an intersection of a corresponding alpha track and a corresponding beta track.

Abstract: An integrated circuit includes a first and second active region, a first and second contact, a first conductor and a first insulating region. The first active region extends in a first direction, is on a first level above a front-side of a substrate, and corresponds to a first set of transistors. The second active region extends in the first direction, is on a second level, and corresponds to a second set of transistors. The first contact extends in a second direction, is on a third level, and overlaps the first active region. The second contact extends in the second direction, is on a fourth level, overlaps the second active region. The first conductor extends in the first direction, is on the third level and the fourth level, and is coupled to the first contact and the second contact. The first insulating region is within a recess of the first conductor.