Patents by Inventor Chi-Yu Lu

Chi-Yu Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7796610
    Abstract: A pipeline scheduler provides a minimum bandwidth guarantee by transporting cells from an input port to an output port in a two-phased approach. Cells that conform to a minimum cell rate (MCR) are selected from queues at the input port and arranged into supercells for transport to the output port, followed by nonconforming cells, to guarantee fairness by using scheduling modules to build the supercells first for conforming cells, and then for nonconforming cells. Reservation vectors are used to permit the same time slot of the next frame to be reserved by a first queue, and the same time slot of the following time frame to be held for reservation by a second queue, to ensure equal time slot access by the first and second queues over successive time frames.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: September 14, 2010
    Assignee: Juniper Networks, Inc.
    Inventors: Ruixue Fan, Chi-Yu Lu
  • Publication number: 20090135832
    Abstract: A pipeline scheduler provides a minimum bandwidth guarantee by transporting cells from an input port to an output port in a two-phased approach. Cells that conform to a minimum cell rate (MCR) are selected from queues at the input port and arranged into supercells for transport to the output port, followed by nonconforming cells, to guarantee fairness by using scheduling modules to build the supercells first for conforming cells, and then for nonconforming cells. Reservation vectors are used to permit the same time slot of the next frame to be reserved by a first queue, and the same time slot of the following time frame to be held for reservation by a second queue, to ensure equal time slot access by the first and second queues over successive time frames.
    Type: Application
    Filed: January 28, 2009
    Publication date: May 28, 2009
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: Ruixue FAN, Chi-Yu LU
  • Patent number: 7499454
    Abstract: A pipeline scheduler provides a minimum bandwidth guarantee by transporting cells from an input port to an output port in a two-phased approach. Cells that conform to a minimum cell rate (MCR) are selected from queues at the input port and arranged into supercells for transport to the output port, followed by nonconforming cells, to guarantee fairness by using scheduling modules to build the supercells first for conforming cells, and then for nonconforming cells. Reservation vectors are used to permit the same time slot of the next frame to be reserved by a first queue, and the same time slot of the following time frame to be held for reservation by a second queue, to ensure equal time slot access by the first and second queues over successive time frames.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: March 3, 2009
    Assignee: Juniper Networks, Inc.
    Inventors: Ruixue Fan, Chi-Yu Lu
  • Patent number: 7274713
    Abstract: The present invention provides a system and method for enabling the synchronization of a switch and an interface device. Based on a comparison of cell sequence numbers included in cells received from the interface device to a current cell time within the switch, cell time adjustment information can be transmitted to the interface device. The cell time adjustment information is used by the interface device to determine the cell sequence number that is included in cells transmitted to the switch.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: September 25, 2007
    Assignee: Altera Corporation
    Inventors: James E. Tatem, Jr., Randy A. Drago, Chi-Yu Lu, Son Truong Ngo, Rong Zhang, Vahid Tabatabaee, Kirby Lee Nell
  • Publication number: 20060120286
    Abstract: A pipeline scheduler provides a minimum bandwidth guarantee by transporting cells from an input port to an output port in a two-phased approach. Cells that conform to a minimum cell rate (MCR) are selected from queues at the input port and arranged into supercells for transport to the output port, followed by nonconforming cells, to guarantee fairness by using scheduling modules to build the supercells first for conforming cells, and then for nonconforming cells. Reservation vectors are used to permit the same time slot of the next frame to be reserved by a first queue, and the same time slot of the following time frame to be held for reservation by a second queue, to ensure equal time slot access by the first and second queues over successive time frames.
    Type: Application
    Filed: January 23, 2006
    Publication date: June 8, 2006
    Inventors: Ruixue Fan, Chi-Yu Lu
  • Patent number: 7042883
    Abstract: A pipeline scheduler provides a minimum bandwidth guarantee by transporting cells from an input port to an output port in a two-phased approach. Cells that conform to a minimum cell rate (MCR) are selected from queues at the input port and arranged into supercells for transport to the output port, followed by nonconforming cells, to guarantee fairness by using scheduling modules to build the supercells first for conforming cells, and then for nonconforming cells. Reservation vectors are used to permit the same time slot of the next frame to be reserved by a first queue, and the same time slot of the following time frame to be held for reservation by a second queue, to ensure equal time slot access by the first and second queues over successive time frames.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: May 9, 2006
    Assignee: Juniper Networks, Inc.
    Inventors: Ruixue Fan, Chi-Yu Lu
  • Publication number: 20040042466
    Abstract: The present invention provides a system and method for enabling the synchronization of a switch and an interface device. Based on a comparison of cell sequence numbers included in cells received from the interface device to a current cell time within the switch, cell time adjustment information can be transmitted to the interface device. The cell time adjustment information is used by the interface device to determine the cell sequence number that is included in cells transmitted to the switch.
    Type: Application
    Filed: August 30, 2002
    Publication date: March 4, 2004
    Inventors: James E. Tatem,, Randy A. Drago, Chi-Yu Lu, Son Truong Ngo, Rong Zhang, Vahid Tabatabaee, Kirby Lee Nell
  • Publication number: 20020122428
    Abstract: A pipeline scheduler provides a minimum bandwidth guarantee by transporting cells from an input port to an output port in a two-phased approach. Cells that conform to a minimum cell rate (MCR) are selected from queues at the input port and arranged into supercells for transport to the output port, followed by nonconforming cells, to guarantee fairness by using scheduling modules to build the supercells first for conforming cells, and then for nonconforming cells. Reservation vectors are used to permit the same time slot of the next frame to be reserved by a first queue, and the same time slot of the following time frame to be held for reservation by a second queue, to ensure equal time slot access by the first and second queues over successive time frames.
    Type: Application
    Filed: October 16, 2001
    Publication date: September 5, 2002
    Applicant: NEC USA, INC.
    Inventors: Ruixue Fan, Chi-Yu Lu