Patents by Inventor Chi-Yu YEH

Chi-Yu YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9842891
    Abstract: A pixel circuit is provided comprising the following. The first transistor includes a gate electrode and a semiconductor layer comprising a channel region, a source region, a first drain region, and a second drain region. A first portion of the channel region is connected to the source region, a second portion of the channel region is connected to the first drain region, and a third portion of the channel region is connected to the second drain region. The channel width of the second portion is greater than that of the third portion. A capacitive device is connected to the gate of the first transistor. The second transistor includes a source region connected to the second drain region and a drain region connected to the light-emitting element. The third transistor includes a source region connected to the first drain region and a drain region connected to a capacitive device.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 12, 2017
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chi-Yu Yeh, Chen-Ming Hu, Yen-Shih Huang
  • Publication number: 20170323933
    Abstract: A pixel circuit is provided comprising the following. The first transistor includes a gate electrode and a semiconductor layer comprising a channel region, a source region, a first drain region, and a second drain region. A first portion of the channel region is connected to the source region, a second portion of the channel region is connected to the first drain region, and a third portion of the channel region is connected to the second drain region. The channel width of the second portion is greater than that of the third portion. A capacitive device is connected to the gate of the first transistor. The second transistor includes a source region connected to the second drain region and a drain region connected to the light-emitting element. The third transistor includes a source region connected to the first drain region and a drain region connected to a capacitive device.
    Type: Application
    Filed: July 28, 2017
    Publication date: November 9, 2017
    Inventors: Chi-Yu YEH, Chen-Ming HU, Yen-Shih HUANG
  • Patent number: 9755007
    Abstract: A pixel circuit is provided comprising the following. The first transistor includes a gate electrode and a semiconductor layer comprising a channel region, a source region, a first drain region, and a second drain region. A first portion of the channel region is connected to the source region, a second portion of the channel region is connected to the first drain region, and a third portion of the channel region is connected to the second drain region. The channel width of the second portion is greater than that of the third portion. A capacitive device is connected to the gate of the first transistor. The second transistor includes a source region connected to the second drain region and a drain region connected to the light-emitting element. The third transistor includes a source region connected to the first drain region and a drain region connected to a capacitive device.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: September 5, 2017
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chi-Yu Yeh, Chen-Ming Hu, Yen-Shih Huang
  • Publication number: 20170133447
    Abstract: A pixel circuit is provided comprising the following. The first transistor includes a gate electrode and a semiconductor layer comprising a channel region, a source region, a first drain region, and a second drain region. A first portion of the channel region is connected to the source region, a second portion of the channel region is connected to the first drain region, and a third portion of the channel region is connected to the second drain region. The channel width of the second portion is greater than that of the third portion. A capacitive device is connected to the gate of the first transistor. The second transistor includes a source region connected to the second drain region and a drain region connected to the light-emitting element. The third transistor includes a source region connected to the first drain region and a drain region connected to a capacitive device.
    Type: Application
    Filed: June 14, 2016
    Publication date: May 11, 2017
    Inventors: Chi-Yu YEH, Chen-Ming HU, Yen-Shih HUANG