Abstract: A semiconductor memory and address-decoding circuit and method for decoding address allow the semiconductor memory to operate under a decreased capacity by disabling or hiding a predetermined portion of the semiconductor memory. The semiconductor memory has a first address-inputting circuit configured to receive a first external address, a switching circuit configured to switch a predetermined portion of the first external address to form an internal address, at least one address-setting code configured to set at least one predetermined bit of the internal address, a decoder coupling to the switching circuit and the address-setting code, and a memory array coupling to the decoder, wherein the decoder is configured to select at least one memory unit of the memory array based on the internal address. The first address-inputting circuit, the switching circuit and the address-setting code can be considered as an address-decoding circuit.

Abstract: A semiconductor memory and address-decoding circuit and method for decoding address allow the semiconductor memory to operate under a decreased capacity by disabling or hiding a predetermined portion of the semiconductor memory. The semiconductor memory comprises a first address-inputting circuit configured to receive a first external address, a switching circuit configured to switch a predetermined portion of the first external address to form an internal address, at least one address-setting code configured to set at least one predetermined bit of the internal address, a decoder coupling to the switching circuit and the address-setting code, and a memory array coupling to the decoder, wherein the decoder is configured to select at least one memory unit of the memory array based on the internal address. The first address-inputting circuit, the switching circuit and the address-setting code can be considered as an address-decoding circuit.