Patents by Inventor Chia-An YEH

Chia-An YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240142684
    Abstract: An electronic device such as a wristwatch may be provided with conductive structures. The conductive structures may include a sensor electrode for an electrocardiogram (ECG) sensor. A coating may be disposed on the sensor electrode to reflect particular wavelengths of visible light so that the sensor electrode exhibits a desired color. The coating may include adhesion and transition layers on the sensor electrode, an opaque coloring layer on the adhesion and transition layers, and a thin-film interference filter on the opaque coloring layer. The thin-film interference filter may have an uppermost diamond-like carbon (DLC) layer. The DLC layer may contribute to the color response of the coating while concurrently minimizing noise in ECG waveforms gathered by the ECG sensor using the sensor electrode.
    Type: Application
    Filed: October 13, 2023
    Publication date: May 2, 2024
    Inventors: Bin Fan, Brian S. Tryon, Xiaofan Niu, Chia-Yeh Lee, Frank C. Sit, Hien Minh H Le, Justin S. Shi, Shinjita Acharya, Ziqing Duan
  • Publication number: 20240113414
    Abstract: Disclosed is an electronic device including a device body and an antenna module. The antenna module includes a conductive element and at least one antenna element. The conductive element includes a main body portion and at least one assembly portion connected with each other. The at least one assembly portion is assembled on the device body. The at least one antenna element is disposed on the device body and coupled with the conductive element to excite a first resonance mode. The at least one assembly portion overlaps the at least one antenna element in the length direction of the main body portion.
    Type: Application
    Filed: September 24, 2023
    Publication date: April 4, 2024
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chih-Heng Lin, Li-Chun Lee, Shih-Chia Liu, Jui-Hung Lai, Hung-Yu Yeh
  • Patent number: 11946087
    Abstract: Provided herein are compositions and methods for co-production and recovery of two or more isoprenoids from a single recombinant cell.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: April 2, 2024
    Assignee: AMYRIS BIO PRODUCTS PORTUGAL, UNIPESSOAL, LDA
    Inventors: Christopher J. Paddon, Victor Holmes, Chia-Hong Tsai, Yoseph Tsegaye, Phoebe Yeh
  • Publication number: 20240106104
    Abstract: An electronic device includes a device body and an antenna module disposed in the device body and including a conductive structure and a coaxial cable including a core wire, a shielding layer wrapping the core wire, and an outer jacket wrapping the shielding layer. The conductive structure includes a structure body and a slot formed on the structure body and penetrating the structure body in a thickness direction of the structure body. A section of the shielding layer extends from the outer jacket and is connected to the structure body. A physical portion of the structure body and the section of the shielding layer are respectively located on two opposite sides of the slot in a width direction of the slot. A section of the core wire extends from the section of the shielding layer and overlaps the slot and the physical portion in the thickness direction.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 28, 2024
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Hung-Yu Yeh, Shih-Chia Liu, Yen-Hao Yu, Li-Chun Lee, Chih-Heng Lin, Jui-Hung Lai
  • Publication number: 20240105778
    Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: I-Sheng CHEN, Yee-Chia YEO, Chih Chieh YEH, Cheng-Hsien WU
  • Publication number: 20240088061
    Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Shu-Shen Yeh, Che-Chia Yang, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
  • Publication number: 20240088267
    Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi PENG, Chih Chieh YEH, Chih-Sheng CHANG, Hung-Li CHIANG, Hung-Ming CHEN, Yee-Chia YEO
  • Patent number: 11930174
    Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 12, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Tzu-Der Chuang, Chih-Wei Hsu, Ching-Yeh Chen, Zhi-Yi Lin
  • Patent number: 11924444
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream corresponding to compressed data including the current block in the current picture at a video decoder side, and determines a first boundary associated with the current block, wherein the first boundary corresponds to one vertical boundary or one horizontal boundary of the current block. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a filtered-reconstructed current block, using a plurality of first reference samples at a same side of the first boundary, and replaces a first set of the first reference samples by one or more padding values. The method then generates a filtered decoded picture including the filtered-reconstructed current block.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 5, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Publication number: 20240072552
    Abstract: A power-saving charging device controls both a primary side controller and a secondary side controller to be in a shutdown state when an output terminal is not connected to the load. When the output terminal is connected to the load, the secondary side controller receives a power-on power supply from a power storage unit, performs a power-on procedure and enters a working state. The primary side controller receives a power-on signal from the power storage unit, performs the power-on procedure according to the power-on signal, and enters the working state. Accordingly, when the charging device is not connected to the load, it can enter a standby state with extremely low power consumption in which the primary side controller and the secondary side controller are both turned off, thereby achieving the effect of saving the power consumption of the controller when the charging device is in standby.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Chia-An YEH, Wei-Liang LIN
  • Patent number: 11916031
    Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
  • Patent number: 11885987
    Abstract: The present invention discloses a quantum-dot film, wherein the quantum-dot film comprises a binder and a plurality of quantum dots dispersed in the binder, wherein the plurality of quantum dots are capable of being water-resistant and oxygen-resistant.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: January 30, 2024
    Assignee: UBRIGHT OPTRONICS CORPORATION
    Inventors: Chia-Yeh Miu, Ge-Wei Lin, Chia-Jung Chiang, Chien-Chih Lai, Lung-Pin Hsin, Yi-Long Tyan, Jeffrey Wu, Hui-Yong Chen, Ying-Yi Lu
  • Publication number: 20230288609
    Abstract: An optical structure, comprising an optical film having a substrate, wherein a first plurality of multi-faceted recesses are formed on the top surface of the substrate, wherein a prism module is disposed over the first optical film, wherein the prism module comprises a plurality of prism sheets that are stacked and bonded to each other.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 14, 2023
    Inventors: CHING-AN YANG, Lung-Pin Hsin, Hui-Yong Chen, Chien-Chih Lai, Yu-Mei Juan, Chia-Yeh Miu, Ge-Wei Lin, Ming Te Huang, CHENG CHIEH CHIU, WEN JEN WU
  • Publication number: 20230235973
    Abstract: A guidance unit comprises a first pipe part and a second pipe part, an inner space diameter of the second pipe part is smaller than an inner space diameter of the first pipe part, causing a cross-sectional area of a second flow space perpendicular to a pipe axis of the second pipe part smaller than that of a first flow space perpendicular to a pipe axis of the first pipe part; one end of the pipe axis of the second pipe part and one end of the pipe axis of the first pipe part are connected in series with each other and spaced apart from each other by a first angle, so that the second flow space communicates with the first flow space; thereby, a pressure of an external fluid in the second flow space is greater than a pressure of the external fluid in the first flow space.
    Type: Application
    Filed: February 16, 2022
    Publication date: July 27, 2023
    Inventors: Kuo-wei CHIU, Chia-An Yeh
  • Publication number: 20230168416
    Abstract: An optical film, comprising a substrate, wherein a first plurality of multi-faceted recesses are formed on the substrate, wherein the plurality of multi-faceted recesses are capable of scattering lights that enter into a second surface of the substrate, said first surface and said second surface are two opposite surfaces of the substrate.
    Type: Application
    Filed: October 28, 2022
    Publication date: June 1, 2023
    Inventors: CHING-AN YANG, Lung-Pin Hsin, Hui-Yong Chen, Chien-Chih Lai, Yu-Mei Juan, Chia-Yeh Miu, Ge-Wei Lin, Ming Te Huang, CHENG CHIEH CHIU, WEN JEN WU
  • Patent number: 11658581
    Abstract: A power converter with an adjustable output voltage has an isolation DC/DC transformer, a primary side circuit connected to a primary coil of the isolation DC/DC transformer for transmitting an input AC power to the primary coil, and a secondary side circuit connected to a secondary coil of the isolation DC/DC transformer. The secondary side circuit includes a first output loop, a second output loop and a mode switch connected in the first output loop. When power consumption of a load is low, the mode switch is turned off to interrupt the first output loop so that the secondary side circuit generates a first output voltage with a low voltage level. When power consumption of a load is high, the mode switch is turned on and the secondary side circuit generates a second output voltage with a high voltage level. Without greatly increasing circuits, the power converter achieves wide-range voltage regulation.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: May 23, 2023
    Assignee: Acbel Polytech Inc.
    Inventor: Chia-An Yeh
  • Publication number: 20230149544
    Abstract: Provided herein are methods of treating or preventing a T-cell mediated inflammatory disease or cancer in a subject in need thereof comprising administering to the subject a therapeutically effective amount of an antibody that specifically binds to human PSGL-1 in combination with a Janus kinase (JAK) inhibitor. In some embodiments, the T-cell mediated inflammatory disease is GVHD, e.g., acute GVHD or chronic GVHD.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 18, 2023
    Applicant: AltruBio Inc.
    Inventors: Shih-Yao LIN, Feng-Lin CHIANG, You-Chia YEH
  • Publication number: 20230139182
    Abstract: A composite optical film, comprising: a quantum-dot film and a first optical film disposed over the quantum-dot film, wherein a first plurality of multi-faceted recesses are formed on a first surface of the first optical film, wherein each multi-faceted recess comprises a shape of a reversed cone.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 4, 2023
    Inventors: Chia-Yeh Miu, Lung-Pin Hsin, Hui-Yong Chen, Chia-Jung Chiang, Ge-Wei Lin, Ying-Yi Lu, Chien-Chih Lai, CHING-AN YANG, Yu-Mei Juan
  • Patent number: 11581730
    Abstract: The power supply device with multiple outputs includes two output ports, a power converting module with two power output ends, and two switching modules connected among the two power output ends and the two output ports. The output power from the two power output ends can be independently allocated to either one or two of the two second output ports. When one of the output ports requests for a demand power, the power supply device is able to determine which one or both of the power output ends to output power to the output port, reaching a better power allocation efficiency.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: February 14, 2023
    Assignee: ACBEL POLYTECH INC.
    Inventor: Chia-An Yeh
  • Publication number: 20230043944
    Abstract: The present invention discloses a quantum-dot composite film comprising: a quantum-dot prism film, comprising a quantum-dot layer and a first plurality of prisms disposed over the quantum-dot layer, wherein a first optical prism film and a second optical prism film are disposed over the quantum-dot prism film for increasing the brightness level of the quantum-dot prism film.
    Type: Application
    Filed: November 29, 2021
    Publication date: February 9, 2023
    Inventors: Chia-Yeh Miu, Yu-Mei Juan, Chia-Jung Chiang, Ge-Wei Lin, Ying-Yi Lu, Hui-Yong Chen, Lung-Pin Hsin, Jeffrey Wu