Patents by Inventor Chia-Ao Chang

Chia-Ao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387273
    Abstract: A system and methods of manufacturing semiconductor devices is described herein. The method includes forming a recess between fins in a substrate and forming a dielectric layer over the fins and in the recess. Once the dielectric layer has been formed, a bottom seed structure is formed over the dielectric layer within the recess and the dielectric layer is exposed along sidewalls of the recess. A dummy gate material is grown from the bottom seed structure in a bottom-up deposition process without growing the dummy gate material from the dielectric layer exposed along sidewalls of the recess.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Chia-Ao Chang, Pei-Ren Jeng, Chii-Horng Li, Yee-Chia Yeo
  • Patent number: 11710777
    Abstract: A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ao Chang, De-Wei Yu, Chii-Horng Li, Yee-Chia Yeo, Hsueh-Chang Sung, Pei-Ren Jeng
  • Publication number: 20230215738
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Patent number: 11605543
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Publication number: 20220344490
    Abstract: A system and methods of manufacturing semiconductor devices is described herein. The method includes forming a recess between fins in a substrate and forming a dielectric layer over the fins and in the recess. Once the dielectric layer has been formed, a bottom seed structure is formed over the dielectric layer within the recess and the dielectric layer is exposed along sidewalls of the recess. A dummy gate material is grown from the bottom seed structure in a bottom-up deposition process without growing the dummy gate material from the dielectric layer exposed along sidewalls of the recess.
    Type: Application
    Filed: April 21, 2021
    Publication date: October 27, 2022
    Inventors: Chia-Ao Chang, Pei-Ren Jeng, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20220172958
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Application
    Filed: February 18, 2022
    Publication date: June 2, 2022
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Publication number: 20220130979
    Abstract: A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Inventors: Chia-Ao Chang, De-Wei Yu, Chii-Horng Li, Yee-Chia Yeo, Hsueh-Chang Sung, Pei-Ren Jeng
  • Patent number: 11289343
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Patent number: 11211470
    Abstract: An improved dummy gate and a method of forming the same are disclosed. In an embodiment, the method includes depositing a first material in a trench, the trench being disposed between a first fin and a second fin; etching the first material to expose an upper portion of sidewalls of the trench; and depositing a second material on the first material without the second material being deposited on the exposed upper portion of the sidewalls of the trench.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Ku Chen, Chii-Horng Li, Cheng-Po Chau, Pei-Ren Jeng, Yee-Chia Yeo, Chia-Ao Chang
  • Patent number: 11205709
    Abstract: Embodiments disclosed herein relate generally to forming a structure, e.g., in high aspect ratio trenches. In an embodiment, a method for semiconductor processing is provided. The method includes forming fins on a substrate. Sidewalls of the fins and a bottom surface between the sidewalls of the fins define a trench therebetween. The method includes forming a gate structure over the fins. The gate structure has a sidewall with a defect region formed therein. The method includes forming a filling layer to fill the defect region in the sidewall of the gate structure.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ao Chang, Chien-Hao Chen, De-Wei Yu, Yung-Cheng Lu
  • Publication number: 20210119013
    Abstract: An improved dummy gate and a method of forming the same are disclosed. In an embodiment, the method includes depositing a first material in a trench, the trench being disposed between a first fin and a second fin; etching the first material to expose an upper portion of sidewalls of the trench; and depositing a second material on the first material without the second material being deposited on the exposed upper portion of the sidewalls of the trench.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventors: Meng-Ku Chen, Chii-Horng Li, Cheng-Po Chau, Pei-Ren Jeng, Yee-Chia Yeo, Chia-Ao Chang
  • Publication number: 20200035506
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Application
    Filed: October 4, 2019
    Publication date: January 30, 2020
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Publication number: 20190393325
    Abstract: Embodiments disclosed herein relate generally to forming a structure, e.g., in high aspect ratio trenches. In an embodiment, a method for semiconductor processing is provided. The method includes forming fins on a substrate. Sidewalls of the fins and a bottom surface between the sidewalls of the fins define a trench therebetween. The method includes forming a gate structure over the fins. The gate structure has a sidewall with a defect region formed therein. The method includes forming a filling layer to fill the defect region in the sidewall of the gate structure.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Chia-Ao Chang, Chien-Hao Chen, De-Wei Yu, Yung-Cheng Lu
  • Patent number: 10504747
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Publication number: 20190103284
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Patent number: 10115639
    Abstract: A method may include depositing a first conductive material in an opening disposed between a first semiconductor structure and a second semiconductor structure, the first conductive material comprising at least one first void. The method further includes removing a portion of the first conductive material to form a trench, the trench exposing the at least one first void and being defined by a remaining portion of the first conductive material; and depositing a second conductive material in the trench, the second conductive material and the remaining portion of the first conductive material forming a dummy gate layer.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping Hung Li, Lun-Kuang Tan, Hui-Ying Lu, Chia-Ao Chang
  • Publication number: 20180151693
    Abstract: A method may include depositing a first conductive material in an opening disposed between a first semiconductor structure and a second semiconductor structure, the first conductive material comprising at least one first void. The method further includes removing a portion of the first conductive material to form a trench, the trench exposing the at least one first void and being defined by a remaining portion of the first conductive material; and depositing a second conductive material in the trench, the second conductive material and the remaining portion of the first conductive material forming a dummy gate layer.
    Type: Application
    Filed: January 20, 2017
    Publication date: May 31, 2018
    Inventors: Ping Hung Li, Lun-Kuang Tan, Hui-Ying Lu, Chia-Ao Chang