Patents by Inventor Chia-Che Chuang

Chia-Che Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9321224
    Abstract: An infrared absorption film includes a polymer resin substrate, a polymer dispersant and an infrared absorption material. The infrared absorption material has a plurality of tungsten oxide and/or composite tungsten oxide nanoparticles dispersed in the polymer resin substrate by the polymer dispersant, wherein a weight ratio of the polymer dispersant to the infrared absorption material is between 0.3 and 0.6.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: April 26, 2016
    Assignee: TAIFLEX Scientific Co., Ltd.
    Inventors: Chia-Che Chuang, Yu-Chih Kao, Chen-Kuo Lu, Kuan-Yu Li, Tzu-Ching Hung, Chiu-Feng Chen
  • Publication number: 20160067932
    Abstract: An infrared absorption film includes a polymer resin substrate, a polymer dispersant and an infrared absorption material. The infrared absorption material has a plurality of tungsten oxide and/or composite tungsten oxide nanoparticles dispersed in the polymer resin substrate by the polymer dispersant, wherein a weight ratio of the polymer dispersant to the infrared absorption material is between 0.3 and 0.6.
    Type: Application
    Filed: October 15, 2014
    Publication date: March 10, 2016
    Inventors: Chia-Che Chuang, Yu-Chih Kao, Chen-Kuo Lu, Kuan-Yu Li, Tzu-Ching Hung, Chiu-Feng Chen
  • Publication number: 20140370263
    Abstract: A plasticizable heat-insulating composition compatible with polyvinyl acetal resins and mixed with polyvinyl acetal resin for forming a mixture for a plasticizing process for making a transparent intermediate heat-insulating sheet, as well as a transparent heat-insulating sandwich-structured panel that demonstrates high transparency, high wide-range near infrared absorbance and high heat-insulation index, so as to improve their heat-insulating and energy-saving functions.
    Type: Application
    Filed: September 5, 2013
    Publication date: December 18, 2014
    Applicant: Taiflex Scientific Co., Ltd.
    Inventors: Chen-Kuo LU, Yu-Chih KAO, Chia-Che CHUANG, Tzu-Ching HUNG
  • Patent number: 8021566
    Abstract: An apparatus and method suitable for the pre-conditioning of a polishing pad on a CMP apparatus prior to the polishing of production wafers on the apparatus. The apparatus includes a pre-conditioning arm on which is mounted an ingot of suitable material. In use, the ingot is pressed against the polishing surface of the rotating polishing pad for a selected period of time to increase the temperature of the polishing surface by friction. The pre-conditioned polishing pad facilitates uniform polishing rates of production semiconductor wafers subsequently polished on the apparatus.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: September 20, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Che Chuang, Wen-Chih Chiou, Hsin-Hsien Lu, Liang-Guang Chen
  • Publication number: 20060270237
    Abstract: An apparatus and method suitable for the pre-conditioning of a polishing pad on a CMP apparatus prior to the polishing of production wafers on the apparatus. The apparatus includes a pre-conditioning arm on which is mounted an ingot of suitable material. In use, the ingot is pressed against the polishing surface of the rotating polishing pad for a selected period of time to increase the temperature of the polishing surface by friction. The pre-conditioned polishing pad facilitates uniform polishing rates of production semiconductor wafers subsequently polished on the apparatus.
    Type: Application
    Filed: August 2, 2006
    Publication date: November 30, 2006
    Inventors: Chia-Che Chuang, Wen-Chih Chiou, Hsin-Hsien Lu, Liang-Guang Chen
  • Patent number: 7105446
    Abstract: An apparatus and method suitable for the pre-conditioning of a polishing pad on a CMP apparatus prior to the polishing of production wafers on the apparatus. The apparatus includes a pre-conditioning arm on which is mounted an ingot of suitable material. In use, the ingot is pressed against the polishing surface of the rotating polishing pad for a selected period of time to increase the temperature of the polishing surface by friction. The pre-conditioned polishing pad facilitates uniform polishing rates of production semiconductor wafers subsequently polished on the apparatus.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: September 12, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Che Chuang, Wen-Chih Chiou, Hsin-Hsien Lu, Liang-Guang Chen
  • Publication number: 20050106872
    Abstract: An oxide polishing process that is part of a CMP process flow is disclosed. After a copper layer is polished at a first polishing station and a diffusion barrier layer is polished at a second polishing station, a key sequence at a third polish station is the application of a first oxide slurry and a first DI water rinse followed by a second oxide slurry and then a second DI water rinse. As a result, defect counts are reduced from several thousand to less than 100. Another important factor is a low down force that enables more efficient particle removal. The improved oxide polishing process has the same throughput as a single oxide polish and a DI water rinse method and may be implemented in any three slurry copper CMP process flow.
    Type: Application
    Filed: November 17, 2003
    Publication date: May 19, 2005
    Inventors: William Hong, Chia-Che Chuang, Chi-Wei Chung, Wen-Chih Chiou, Ying-Ho Chen, Syun-Ming Jang
  • Publication number: 20050051266
    Abstract: An apparatus and method suitable for the pre-conditioning of a polishing pad on a CMP apparatus prior to the polishing of production wafers on the apparatus. The apparatus includes a pre-conditioning arm on which is mounted an ingot of suitable material. In use, the ingot is pressed against the polishing surface of the rotating polishing pad for a selected period of time to increase the temperature of the polishing surface by friction. The pre-conditioned polishing pad facilitates uniform polishing rates of production semiconductor wafers subsequently polished on the apparatus.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 10, 2005
    Inventors: Chia-Che Chuang, Wen-Chih Chiou, Hsin-Hsien Lu, Liang-Guang Chen
  • Patent number: 6803310
    Abstract: Perform an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on the barrier layer, wherein the atomic layer deposition comprises: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, is transported on the barrier layer; next, perform a purge/vacuum process; then a reactive gas, such as WF6, is transported to form the continuous metal seed layer (CMSL); the cycle step of the atomic layer deposition (ALD) can be repeated to form the thickness of the continuous metal seed layer (CMSL) about 20 to 40 Å.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: October 12, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Piao Wang, Chia-Che Chuang
  • Patent number: 6787461
    Abstract: Perform an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on the barrier layer, wherein the atomic layer deposition comprises: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, is transported on the barrier layer; next, perform a purge/vacuum process; then a reactive gas, such as WF6, is transported to form the continuous metal seed layer (CMSL); the cycle step of the atomic layer deposition (ALD) can be repeated to form the thickness of the continuous metal seed layer (CMSL) about 20 to 40 Å.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: September 7, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Piao Wang, Chia-Che Chuang
  • Patent number: 6686278
    Abstract: A method for forming a plug metal layer is disclosed and includes the following steps. Performance of an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on a barrier layer, wherein the atomic layer deposition comprise: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, being transported on the barrier layer. Next, performance of a purge/vacuum process. Then transporting a reactive gas, such as WF6, to form the continuous metal seed layer (CMSL). A subsequent cycle step of atomic layer deposition (ALD) can be repeated to form the thickness of the continuous metal seed layer (CMSL) to about 20 to 40 Å.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: February 3, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Piao Wang, Chia-Che Chuang
  • Publication number: 20030190802
    Abstract: Perform an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on the barrier layer, wherein the atomic layer deposition comprises: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, is transported on the barrier layer; next, perform a purge/vacuum process; then a reactive gas, such as WF6, is transported to form the continuous metal seed layer (CMSL); the cycle step of the atomic layer deposition (ALD) can be repeated to form the thickness of the continuous metal seed layer (CMSL) about 20 to 40 Å.
    Type: Application
    Filed: March 3, 2003
    Publication date: October 9, 2003
    Applicant: United Microelectronics Corp.
    Inventors: Yu-Piao Wang, Chia-Che Chuang
  • Publication number: 20030124787
    Abstract: Perform an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on the barrier layer, wherein the atomic layer deposition comprises: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, is transported on the barrier layer; next, perform a purge/vacuum process; then a reactive gas, such as WF6, is transported to form the continuous metal seed layer (CMSL); the cycle step of the atomic layer deposition (ALD) can be repeated to form the thickness of the continuous metal seed layer (CMSL) about 20 to 40 Å.
    Type: Application
    Filed: December 17, 2002
    Publication date: July 3, 2003
    Applicant: United Microelectronics Corp.
    Inventors: Yu-Piao Wang, Chia-Che Chuang
  • Publication number: 20020192953
    Abstract: Perform an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on the barrier layer, wherein the atomic layer deposition comprises: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, is transported on the barrier layer; next, perform a purge/vacuum process; then a reactive gas, such as WF6, is transported to form the continuous metal seed layer (CMSL); the cycle step of the atomic layer deposition (ALD) can be repeated to form the thickness of the continuous metal seed layer (CMSL) about 20 to 40 Å.
    Type: Application
    Filed: June 19, 2001
    Publication date: December 19, 2002
    Inventors: Yu-Piao Wang, Chia-Che Chuang