Patents by Inventor Chia Chen

Chia Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180350664
    Abstract: A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.
    Type: Application
    Filed: November 1, 2017
    Publication date: December 6, 2018
    Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Chun-Hung Chao, Yu-Li Cheng
  • Publication number: 20180352223
    Abstract: A reduced merge candidate signaling method is provided. When building a merge candidate list for a prediction unit (PU) of a block of pixels, a video codec skips or partially skips the construction of some sub-PU merge candidates. The video codec then performs simplified pruning operations on the merge candidate list based on the skipped or partially constructed sub-PU merge candidates. The pruned candidate list is then used to select a merge candidate to encode or decode the block of pixels.
    Type: Application
    Filed: May 29, 2018
    Publication date: December 6, 2018
    Inventors: Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen
  • Publication number: 20180348264
    Abstract: A voltage selection circuit includes: a power detection circuit configured to compare an output voltage with a first input voltage and a second input voltage, respectively; a latch circuit, coupled to the power detection circuit, and configured to flip respective logic states of a pair of output signals when the output voltage is lower than either the first input voltage or the second input voltage; and a selection circuit, coupled to the latch circuit, and configured to use either the first input voltage or the second input voltage as the output voltage based on the respective logic states of the pair of output signals.
    Type: Application
    Filed: March 30, 2018
    Publication date: December 6, 2018
    Inventors: Chia-Chen KUO, Chiting CHENG, Wei-Jer HSIEH
  • Publication number: 20180351300
    Abstract: The present disclosure describes an electronic device, including: a card holder, a card tray, a processing chip, and an unlocking structure, where a slot that accommodates the card tray is disposed on the card holder, and at least one locking structure is disposed in the slot; the unlocking structure includes an electromagnet, the unlocking structure is connected to the processing chip, the card tray is configured to accommodate a card of the electronic device, and at least one locking part that fits the locking structure is disposed on the card tray; and the processing chip is configured to: in response to a card removal operation signal being received, verify a user identity, and in response to the user identity verification succeeding, control the unlocking structure to release the card tray.
    Type: Application
    Filed: November 23, 2015
    Publication date: December 6, 2018
    Inventors: Xin ZHU, Chia Huan CHANG, Mingjun CHEN, Tianhua LIU, Gaobing LEI
  • Publication number: 20180348032
    Abstract: An optical flow sensing method includes: using an image sensor to capture images; using a directional-invariant filter device upon at least one first block of the first image to process values of pixels of the at least one first block of the first image, to generate a first filtered block image; using the first directional-invariant filter device upon at least one first block of the second image to process values of pixels of the at least one first block of the second image, to generate a second filtered block image; comparing the filtered block images to calculate a correlation result; and estimating a motion vector according to a plurality of correlation results.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Hsin-Chia Chen, Sen-Huang Huang, Wei-Chung Wang, Chao-Chien Huang, Ting-Yang Chang, Chun-Wei Chen
  • Publication number: 20180350606
    Abstract: Methods for forming 3D-NAND devices comprising recessing a poly-Si layer to a depth below a spaced oxide layer. A liner is formed on the spaced oxide layer and not on the recessed poly-Si layer. A metal layer is deposited in the gaps on the liner to form wordlines.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 6, 2018
    Inventors: Yihong Chen, Yong Wu, Chia Cheng Chin, Xinliang Lu, Srinivas Gandikota, Ziqing Duan, Abhijit Basu Mallick
  • Patent number: 10148994
    Abstract: A mirroring transmission method is provided. The present method retrieves image frames and audio signals of a transmitter and transmits the retrieved image frames and retrieved audio signals to a receiver to be displayed wirelessly. In the meantime, the present method monitors status of a network connected with the transmitter and the receiver, and determines if the network is stable or not. Also, the method stops retrieving and transmitting the audio signal from the transmitter to the receiver, and controls the transmitter to display the audio signal directly through an internal audio module whenever the network is determined unstable.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: December 4, 2018
    Assignee: BARCO LIMITED
    Inventors: Kuan-Yu Chou, Shih-Ping Liu, Cheng-Hsiung Chang, Yen-Hsiang Wang, Chia-Chen Kuo
  • Patent number: 10146212
    Abstract: A machine tool feed drive design system is provided, which may include a component database, a detection module, a load condition estimation module and a calculation module. The component database may store the specification data of a plurality of feed drive components. The detection module may detect a plurality of operation signals from a machine tool during a period of time when the machine tool had been executing a machining process to a workpiece. The load condition estimation module may calculate a plurality of actual load conditions according to the operation signals and a device specification parameter of a feed drive of the machine tool. The calculation module may select at least one component combination from the feed drive components according to the actual load conditions and the specification data of the feed drive components to serve as an optimized feed drive specification.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 4, 2018
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Pei Wang, Chien-Chih Liao, Hsiao-Chen Ho, Jen-Ji Wang
  • Patent number: 10139947
    Abstract: A touch-sensing device is provided, which includes a substrate with a central region and a peripheral region, and a first light-shielding layer disposed on the peripheral region, wherein the first light-shielding layer has a first edge adjacent to the central region. The device further includes a touch-sensing layer disposed on the central region, and a part of the touch-sensing layer extends onto the peripheral region to cover a part of the first light-shielding layer. The device also includes a conductive line layer disposed on the first light-shielding layer, and a second light-shielding layer covering at least a part of the first light-shielding layer and at least a part of the conductive line layer. The second light-shielding layer has a second edge adjacent to the central region, and the second edge has a profile roughness that is greater than that of the first edge.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: November 27, 2018
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Hsiung Chang, Yang-Chen Chen, Kuo-Chang Su, Hsia-Ching Chu
  • Patent number: 10141266
    Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Wei-Chung Hsiao, Shih-Chao Chiu, Chun-Hsien Lin, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20180337100
    Abstract: A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Bo-Yu Lai, Bo-Cyuan Lu, Chi On Chui, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20180334647
    Abstract: A target particle transferring device is disclosed, which comprises: (a) a substrate with a thickness of T and a width of W, having top and bottom portions, the top portion having a top surface and the bottom portion having a bottom surface; (b) a notch structure formed in the bottom portion of the substrate, comprising: a groove with a width of W1, located at a distance oft below the top surface of the substrate, wherein the groove is formed in the bottom portion from the bottom surface extending toward the top portion; and (c) a target substrate portion with a width of W2 and a thickness of T, located in the top and bottom portions of the substrate and being surrounded by the groove. Methods of transferring a target particle from one device to another is also disclosed.
    Type: Application
    Filed: November 18, 2016
    Publication date: November 22, 2018
    Inventors: Chia-Hsien S. Hsu, Ching-Hui Lin, Duane S. Juang, Hao-Chen Chang
  • Patent number: 10134843
    Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Sheng Chen, Chih Chieh Yeh, Cheng-Hsien Wu, Yee-Chia Yeo
  • Patent number: 10134861
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure and a second fin structure disposed over the substrate. The semiconductor device structure includes a first gate stack overlapping the first fin structure. The first gate stack has a first width. The first gate stack includes a first work function layer. A first top surface of the first work function layer is positioned above the first fin structure by a first distance. The semiconductor device structure includes a second gate stack disposed overlapping the second fin structure. The first width is less than a second width of the second gate stack. A second top surface of a second work function layer of the second gate stack is positioned above the second fin structure by a second distance. The first distance is less than the second distance.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Han Fang, Chang-Yin Chen, Ming-Chia Tai, Po-Chi Wu
  • Patent number: 10134107
    Abstract: A data arrangement method includes following steps: obtaining pixel data of a plurality of first N-bit pixels of a picture; and storing the obtained pixel data of the first N-bit pixels in a plurality of M-bit storage units of a first buffer according to a block-based scan order of the picture. The picture includes a plurality of data blocks, and the block-based scan order includes a raster-scan order for the data blocks. At least one of the M-bit storage units is filled with part of the obtained pixel data of the first N-bit pixels, M and N are positive integers, M is not divisible by N, and the first N-bit pixels include at least one pixel divided into a first part stored in one of the M-bit storage units in the first buffer and a second part stored in another of the M-bit storage units in the first buffer.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: November 20, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chun-Chia Chen, Chi-Cheng Ju, Yung-Chang Chang, Ping Chao
  • Patent number: 10134709
    Abstract: A light emitting diode package including a circuit layer, a light-shielding layer, a plurality of light emitting diodes and an encapsulation layer is provided. A thickness of the circuit layer is less than 100 ?m. The light-shielding layer is disposed on a first surface of the circuit layer and the light-shielding layer has a plurality of apertures. The light emitting diodes are disposed on the first surface of the circuit layer and in the apertures of the light-shielding layer. The light emitting diodes are electrically connected to the circuit layer. The encapsulation layer covers the light-shielding layer. A refractive index of the encapsulation layer is 1.4 and to 1.7. The Young's modulus of the encapsulation layer is larger than or equal to 1 GPa. A thickness of the encapsulation layer is greater than thicknesses of the light emitting diodes.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 20, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Hsien Wu, Yao-Jun Tsai, Chia-Hsin Chao, Yen-Hsiang Fang, Yi-Chen Lin, Ching-Ya Yeh
  • Patent number: 10133425
    Abstract: A touch device is provided, including a first substrate and a circuit board. The first substrate includes a touch sensing structure and a plurality of first electrodes. The touch sensing structure is disposed on the first substrate. The first electrodes are arranged along a first direction. The first electrodes are disposed on the first substrate and electrically connected to the touch sensing structure, a first gap is formed between two adjacent first electrodes, and a minimum distance between the two adjacent first electrodes is a gap distance. The circuit board is partially overlapping the substrate in a vertical projection direction, the circuit board including a plurality of second electrodes corresponding to the first electrodes. One of the two adjacent first electrodes has a first electrode side edge facing the first gap. One of the second electrodes has a second electrode side edge located in the first gap.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: November 20, 2018
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Hsiung Chang, Yang-Chen Chen, Kuo-Chang Su, Hsia-Ching Chu
  • Patent number: 10134640
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes a gate structure over the fin portion and extending across the fin portion. The semiconductor device structure includes a first semiconductor wire over the fin portion and passing through the gate structure. The semiconductor device structure includes a second semiconductor wire over the first semiconductor wire and passing through the gate structure. The gate structure surrounds the second semiconductor wire and separates the first semiconductor wire from the second semiconductor wire. The first semiconductor wire and the second semiconductor wire are made of different materials.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Chao-Ching Cheng, Chih-Chieh Yeh, Yee-Chia Yeo
  • Patent number: 10134947
    Abstract: A compound semiconductor device includes a substrate, including a top surface, a bottom surface, a side surface connecting the top surface and the bottom surface; and a semiconductor stack formed on the top surface, wherein the side surface includes a first deteriorated surface, a second deteriorated surface, a first crack surface between the first and second deteriorated surfaces, a second crack surface between the first deteriorated surface and the top surface, and a third crack surface between the second deteriorated surface and the bottom surface, wherein a convex region or a concave region is formed by the first deteriorated surface, the first crack surface and the second crack surface, or the second deteriorated surface, the first crack surface and the third crack surface; and wherein the second crack surface or the third crack surface is substantially perpendicular to the top surface or the bottom surface.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: November 20, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Chia Chen Tsai, Chen Ou, Chi Ling Lee, Chi Shiang Hsu
  • Publication number: 20180328011
    Abstract: A touch free automatic faucet is provided. The faucet includes a faucet housing including many sensors for controlling water flow and water temperature. A processor is connected to the sensors. A first control valve assembly is connected to the processor. A second control valve assembly is connected to the processor. A power source is connected to the processor, the first control valve assembly and the second control valve assembly. Water flow and water temperature are controlled by the sensors without touching of the faucet housing.
    Type: Application
    Filed: December 7, 2017
    Publication date: November 15, 2018
    Inventor: Chung-Chia Chen