Abstract: An anti-fuse structure and a method for forming the anti-fuse structure employ a substrate having formed therein a contact region. A metal silicide layer is formed over and electrically connected with the contact region. A first doped polysilicon layer is formed upon the metal silicide layer. An anti-fuse material layer is formed upon the first doped polysilicon layer. A second doped polysilicon layer is formed upon the anti-fuse material layer. The first doped polysilicon layer and the second doped polysilicon layer may be formed with the same or complementary dopant polarity, the latter providing an anti-fuse diode.

Abstract: A method for fabricating a one time programmable read only memory (OPTROM) device. A first conductive layer, a first semiconductor layer, an anti-fuse layer, a second semiconductor layer are sequentially formed on a substrate. The second semiconductor layer, the anti-fuse layer, the first semiconductor layer, and the first conductive layer are then patterned along the first direction into a first conductive line. The second semiconductor layer, the anti-fuse layer, and the first semiconductor layer are patterned into a memory cell. A dielectric layer is deposited over the substrate, wherein oxygen plasma sputtering is performed to clean the substrate before deposition. A second conductive line is formed over the second dielectric layer, running generally orthogonal to the first conductive line.

Abstract: A method is used to form a borderless via in a semiconductor device. A conductive layer, a borophosphosilicate glass (BPSG) layer and a patterned first mask layer are formed on a dielectric layer in sequence. The BPSG layer is patterned into a BPSG plug while using the patterned first mask layer as a mask. A second mask layer is formed to cover the patterned first mask layer and the metal layer. The conductive layer is defined to form a conductive line beneath the BPSG plug and the second mask layer. The first and second photoresist mask layers are removed. An inter-metal dielectric layer is formed around the BPSG plug and the conductive line. A via is formed in the inter-metal dielectric layer by removing the BPSG plug. A barrier layer and a metal layer fill the via to form a metal plug.

Abstract: A bonding pad structure and its method of manufacture. The structure has a metallic bonding pad with a patterned surface, a first passivation layer having an opening above the metallic bonding pad and a second passivation layer over the first passivation layer also having an opening above the metallic bonding pad. The method of forming the bonding pad structure includes forming a metallic bonding pad over a substrate, and then forming a first passivation layer over the substrate and the bonding pad. The first passivation layer above the bonding pad is patterned. Using the first passivation layer as a mask, a portion of the exposed metal pad material is removed. A patterned second passivation layer is formed over the first passivation layer. The second passivation layer has an opening that exposes the bonding pad. Finally, residual material from the first passivation layer inside the bonding pad region is removed to expose the bonding pad surface.

Abstract: The present invention provides a cell structure of an electrically programmable read only memory (EPROM) which includes an EPROM gate structure, a source junction region, a drain junction region, a first dielectric layer, a self-aligned common source line, a self-aligned drain contact, a second dielectric layer, and a conductive line. The EPROM gate structure is on a portion of the substrate. The source junction region is in the substrate located on a first lateral side, namely the left side in the figure, of the EPROM gate structure. The drain junction region is in the substrate located on a second lateral side, namely the right side in the figure, of the EPROM gate structure. The first dielectric layer covers on top and sidewalls of the EPROM gate structure. The self-aligned common source line neighbors the first dielectric layer and is above the substrate on a portion of the source junction region.

Abstract: A method for manufacturing an erasable programmable memory is disclosed, and an enlargement of the coupling area between control and floating gates is employed to increase the capacitive-coupling ratio. Firstly, the isolation regions are formed on the substrate. A polysilicon layer is formed on a portion of the control region of the substrate to form an uneven silicon surface. An ion implantation is carried out to form the doped tunnel region and the control gate. A tunnel oxide layer and a non-tunnel oxide layer are formed on the doped tunnel region, and an inter-poly dielectric is formed on the control gate. A floating gate is now deposited on the doped tunnel region and the control gate. Then an inter-layer dielectric is formed and etched to provide the isolation and connect between control gate and interconnects.

Abstract: The present invention discloses an EPLD cell includes a semiconductor substrate, tunnel buried layer, control gate, and floating gate. The tunnel buried layer and control gate, which has a three-dimensional contour, are formed under the surface of semiconductor substrate by implanting N-type dopant. The floating gate formed completely over the tunnel buried layer and partially over the control gate, is insulating from them by oxide layers. Because of the three-dimensional contour of control gate, the overlapped area between the floating gate and control gate could be increase without expanding horizontal area of the cell. Therefore, the efficiency of the cell can be improved without degrading the integration in applying the cell.

Abstract: The method includes patterning a first polysilicon layer on a substrate. A first dielectric having a first via hole is defined over the substrate. A second polysilicon layer is formed along the surface of the first dielectric layer and refilled into the first via hole. Then, an etching is used to etch the layer. A residual portion of the layer is located at the lower portion of the first via hole. An undoped polysilicon is then patterned on the first dielectric layer and along the surface of the first via hole. An isolation structure is then refilled into the first via hole. An oxide layer is formed on the first polysilicon, the first dielectric layer and the upper surface of isolation structure to act as the gate oxide of the TFT. Then, the oxide and the first dielectric layer are etched to define a second via hole. A further polysilicon layer is pattern on the first dielectric layer and refilled into the second via hole for defining the gate.

Abstract: A novel vertical poly load device in 4T SRAM and a method for fabricating the same are disclosed. The poly load structure is a vertical device formed on a buried contact. The poly load vertical device is constructed by forming a hollow in a planarized dielectric layer with a high temperature oxide layer on the walls of the hollow and with lightly doped n-type polysilicon in the hollow. The poly load is connected to the respective drain of the driver transistor through the buried contact and to the gate of the respective gate of the other driver transistor through a connecting line. The resistance of the poly load will increase, as the voltage of the buried contact becomes low thereby reducing the standby current.

Abstract: The method includes forming a first polysilicon on a substrate. Subsequently, a first dielectric layer is formed on the first polysilicon. A second polysilicon is pattern on the first dielectric layer, followed by depositing a second dielectric layer formed thereon. An etching is performed to etch the second dielectric layer, the second polysilicon layer through the first dielectric layer for generating an opening. An oxide layer is formed on the side-wall of the opening. A doped polysilicon layer is located at the lower portion of the opening. An undoped polysilicon layer is deposited on the second dielectric layer and refilled into the opening. An etching back is carried out to remove the layer over the second dielectric layer. A third polysilicon is patterned on the surface of the second dielectric layer. An isolation layer is deposited over the feature. A plurality of contact holes are generated in those isolation layers.

Abstract: A method for fabricating alignment marks in a twin-well integrated circuit without using a zero-layer photomask is disclosed.

Abstract: A method of fabricating alignment marks on an integrated circuit device including steps of: forming first pad oxide layer and first nitride layer on a P-type semiconductor substrate; coating and patterning first photoresist layer by lithography; partially etching first nitride layer to form first nitride pattern by first photoresist etching mask; and ion implanting N-type ions to form an N-doped region; coating and patterning second photoresist layer by lithography; partially etching first nitride pattern to form second nitride pattern; and ion implanting P-type ions to formed a P-doped region. Next, performing thermally drive in N-type and P-type impurities to form N-well and P-well regions, and growing an oxide layer simultaneously. Finally, the height difference between the oxide layer and the second nitride pattern producing a ladder topography can be used as an alignment mark for the succeeding lithographic processes.