Patents by Inventor Chia Cheng

Chia Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12243930
    Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Tai Chang, Tung-Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
  • Patent number: 12243918
    Abstract: A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner. The gate structure is on a substrate. The first and second gate spacers are on opposite sides of the gate structure, respectively. The source/drain regions are spaced part from the gate structure at least in part by the first and second gate spacers. The refill metal structure is on the gate structure and between the first and second gate spacers. The first di electric liner is atop the gate structure. The first dielectric liner interposes the refill metal structure and the first gate spacer.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Hsiang Wu, Jia-Chuan You, Chia-Hao Chang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20250065380
    Abstract: A dry cleaning device adapted to clean a container component of a container of a semiconductor manufacturing process and adapted to clean the container component by carbon dioxide snowflakes. The dry cleaning device can first inspect the container component before and after cleaning, clean the container component by carbon dioxide snowflakes according to a predetermined cleaning working set, and forwards the container component to a next workstation once the cleaning of the container component is complete. The dry cleaning device is adapted to clean a container of a semiconductor manufacturing process in a fast and effective manner without involving any liquid solvents.
    Type: Application
    Filed: August 1, 2024
    Publication date: February 27, 2025
    Applicant: GUDENG PRECISION INDUSTRIAL CO., LTD.
    Inventors: MING-CHIEN CHIU, CHIA-HO CHUANG, HSIN-MIN HSUEH, YEN-CHENG TU
  • Publication number: 20250072067
    Abstract: A semiconductor structure includes an isolation structure in a substrate, a metal gate structure over the substrate and a portion of the isolation structure, a spacer at sidewalls of the metal gate structure, epitaxial source/drain structure at two sides of the metal gate structure, and a protection layer over the isolation structure. The protection layer and the spacer include a same material.
    Type: Application
    Filed: August 25, 2023
    Publication date: February 27, 2025
    Inventors: SHIH-CHENG CHEN, WEN-TING LAN, JUNG-HUNG CHANG, CHIA-CHENG TSAI, KUO-CHENG CHIANG
  • Publication number: 20250071289
    Abstract: An image encoder includes a tone mapper, an enhancement layer and an image file generator. The tone mapper is used to generate a base image according to an enhanced image and red green blue (RGB) gains. The RGB gains are set close to or the same as each other. The enhancement layer is used to generate a tone curve and/or a gain map of the base image and the enhanced image according to the tone mapper and/or a group including the base image and the enhanced image. The image file generator is used to generate an image file according to the base image and at least one member of a group including the tone curve and the gain map.
    Type: Application
    Filed: August 22, 2024
    Publication date: February 27, 2025
    Applicant: MEDIATEK INC.
    Inventors: Shou-Ming Chen, Yu-Cheng Chu, Chia-Ying Li
  • Publication number: 20250070092
    Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Wen-Tuo Huang, Chia-Sheng Lin, Wei Chuang Wu, Shih Kuang Yang, Chung-Jen Huang, Shun-Kuan Lin, Chien Lin Liu, Ping-Tzu Chen, Yung Chun Tu
  • Publication number: 20250072065
    Abstract: A device includes: a substrate; a stack of semiconductor channels on the substrate; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; and a hybrid structure between the source/drain region and the substrate. The hybrid structure includes: a first semiconductor layer under the source/drain region; and an isolation region extending vertically from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer.
    Type: Application
    Filed: January 5, 2024
    Publication date: February 27, 2025
    Inventors: Jung-Hung CHANG, Shih-Cheng CHEN, Chia-Hao YU, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250069659
    Abstract: A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.
    Type: Application
    Filed: November 15, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih WANG, Tung-Cheng CHANG, Perng-Fei YUH, Gu-Huan LI, Chia-En HUANG, Chun-Ying LEE
  • Patent number: 12237288
    Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Shu Chia Hsu, Yu-Yun Huang, Wen-Yao Chang, Yu-Jen Cheng
  • Patent number: 12235543
    Abstract: An electronic device is provided. The electronic device includes a frame, a working panel, a case, and an adhesive material. The frame includes a side wall and a back plate. The working panel is disposed on the back plate. The case is disposed on the frame and adjacent to the working panel. The adhesive material is disposed on the case. The side wall has an outer surface facing away from the working panel. In a cross-section view of the electronic device, a portion of the adhesive material is in contact with the outer surface of the side wall of the frame, and a length of the adhesive material is greater than or equal to 50% of a length of the side wall of the frame along an extension direction.
    Type: Grant
    Filed: March 19, 2024
    Date of Patent: February 25, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: Wen-Cheng Huang, Ting-Sheng Chen, Chia-Chun Yang, Chin-Cheng Kuo
  • Patent number: 12234266
    Abstract: The present invention relates to a method for producing CRM197 recombinant protein in cells. The method comprises culturing a cell comprising an expression plasmid with a polynucleotide and inducing expression of the CRM197 protein.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 25, 2025
    Assignee: OBI PHARMA, INC.
    Inventors: I-Ming Cho, Chia-Hung Chiu, Lee-Cheng Liu
  • Publication number: 20250060653
    Abstract: An imaging lens module includes an imaging lens, an adjustable aperture module, a first spacer and a second spacer. The adjustable aperture module is disposed between an object-side lens group and an image-side lens group of the imaging lens and comprises a blade assembly, fixed shafts, a movable component and a driving mechanism. The blade assembly includes at least two light-blocking blades forming a light pass aperture. The driving mechanism is to rotate the movable component in a circumferential direction, allowing the blade assembly to move relative to the fixed shafts for varying an aperture size of the light pass aperture. The fixed shafts are disposed on the first spacer. The second spacer and the first spacer together form an inner space in which the adjustable aperture module is accommodated. The second spacer receives and is in physical contact with the object-side lens group.
    Type: Application
    Filed: January 17, 2024
    Publication date: February 20, 2025
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Te-Sheng TSENG, Chia-Cheng TSAI, Heng Yi SU, Ming-Ta CHOU
  • Publication number: 20250063750
    Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.
    Type: Application
    Filed: November 7, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Yu HUNG, Chia-Cheng Ho, Fei-Yun Chen, Yu-Chang Jong, Puo-Yu Chiang, Tun-Yi Ho
  • Publication number: 20250062139
    Abstract: Embodiments of the present disclosure provide a furnace for semiconductor processing that includes an inner tube defining a reaction chamber and including a sidewall defined along a longitudinal axis of the inner tube and including one or more slits defined through the sidewall in a radial direction with respect to the longitudinal axis. The one or more slits include at least one of a first slit with a width in a range between 10 mm and 100 mm, or a plurality of separate slits with a total number in a range between 2 and 15. The inner tube includes a closed end substantially enclosing the reaction chamber and an open end opposite the closed end with respect to the longitudinal axis. The reaction chamber is configured to be loaded with one or more semiconductor wafers via the open end.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Inventors: De-Wei YU, Chien-Chia CHENG, Ming-Hua YU, Hsueh-Chang SUNG, Chii-Horng LI
  • Publication number: 20250063792
    Abstract: Gate isolation processes (e.g., gate-to-source/drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the CGI opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.
    Type: Application
    Filed: December 1, 2023
    Publication date: February 20, 2025
    Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Chu-Yuan HSU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250063808
    Abstract: A semiconductor structure includes a first dielectric wall over a substrate, and two metal gate structures disposed at two sides of the first dielectric wall. Each of the metal gate structures includes a plurality of nanosheets stacked over the substrate and separated from each other, a high-k gate dielectric layer covering each of the nanosheets, and a metal layer covering and over the plurality of nanosheets and the high-k gate dielectric layer. The high-k gate dielectric layer of each metal gate structure is disposed between the metal layer of each metal gate structure and the first dielectric wall.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Inventors: KUAN-TING PAN, JIA-CHUAN YOU, CHIA-HAO CHANG, KUO-CHENG CHIANG, CHIH-HAO WANG
  • Patent number: 12227839
    Abstract: A sealing article includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Peng-Cheng Hong, Jun-Liang Pu, W. L. Hsu, Chung-Hao Kao, Chia-Chun Hung, Cheng-Yi Wu, Chin-Szu Lee
  • Patent number: 12227759
    Abstract: A temperature-sensitive cell culture composition is provided. The temperature-sensitive cell culture composition includes a hydrogel, a cellulose, a gelatin and a collagen. Based on 1 part by weight of the collagen, a content of the hydrogel is between 0.03 parts by weight and 60 parts by weight, a content of the cellulose is between 150 parts by weight and 360 parts by weight, and a content of the gelatin is between 21 parts by weight and 12 parts by weight. In addition, a method for using the temperature-sensitive cell culture composition, a method for forming the temperature-sensitive cell culture composition, and a use of the temperature-sensitive cell culture composition are also provided.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 18, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Jung Lu, Jing-En Huang, Liang-Cheng Su, Hsin-Hsin Shen, Yuchi Wang, Ying-Hsueh Chao, Li-Hsin Lin, Hsiu-Hua Huang
  • Patent number: 12230338
    Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
    Type: Grant
    Filed: April 4, 2024
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Perng-Fei Yuh, Tung-Cheng Chang, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee, Yih Wang
  • Patent number: D1064033
    Type: Grant
    Filed: April 29, 2024
    Date of Patent: February 25, 2025
    Assignee: Amazon Technologies, Inc.
    Inventors: Wen-Yo Lu, Matthew J. England, Chia-Song Liu, Tsung-Kai Cheng, Ming-Cheng Cheng, Oleksii Krasnoshchok, Oleksii Shekolian, Sergiy Aafanasov, Mikhail Donskoi, Chia-Wei Chan