Abstract: An electrophoresis display with tapered micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The sectional width of the partition wall decreases with a layer number of a polymer stacks forming the partition wall increases.

Abstract: An electrophoresis display with improved micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The height of the partition wall of the micro partition structure is smaller than 25 um.

Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.

Abstract: An electrophoresis display with embedded touch sensing includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer with electrophoresis material, and a touch with display driver (TDDI) electrically connected to data lines and common voltage lines. When the electrophoresis display performs touch sensing operation, the TDDI electrically connected plurality ones of the data lines into single a touch transmitting electrode or a single touch receiving electrode, and the TDDI electrically connected plurality ones of the common voltage lines into a single touch receiving electrode or a single touch transmitting electrode. The viewing face of the electrophoresis display is on the first face of the electrophoresis display.

Abstract: An electrophoresis display with transparent control electrode includes a transparent control substrate having a first face and a second face, a driving circuit layer, a control electrode layer having a plurality of transparent control electrodes, an electrophoresis layer, and an opposite substrate. The charges of the transparent control electrodes attract the charged color particles with opposite polarity to the charges of the transparent control electrodes toward a face of the electrophoresis layer near the control electrodes, thus forming image for viewer.

Abstract: A color electrophoresis display with micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The electrophoresis display further includes a color filter layer arranged on bottom of the chamber. The colloidal solution contains charged black particles and/or charged white particles.

Abstract: An electrophoresis display includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The viewing face of the electrophoresis display is on the first face of the control substrate. The aperture ratio of the control substrate in the electrophoresis display, viewed from the first face of the control substrate and toward a display area of the electrophoresis display, is not less than 70%.

Abstract: An electrophoresis display with storage capacitor having transparent electrode includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The driving circuit layer includes a plurality of storage capacitors. At least the storage capacitors corresponding to the viewing area of the electrophoresis display have a transparent first electrode, a transparent second electrode and an insulating layer between the transparent first electrode and the transparent second electrode.

Abstract: An electrophoresis display with color filter structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The electrophoresis display further includes a color filter layer between the control substrate and the electrophoresis layer. The first face is the viewing face of the electrophoresis display.

Abstract: An electrophoresis display double-side control circuit substrate includes a first control substrate having a first face and a second face, a first driving circuit layer and a first control electrode layer sequentially arranged on the second face, a second control substrate having a third face and a fourth face, a second driving circuit layer and a second control electrode layer sequentially arranged on the third face. The electrophoresis display includes a micro partition structure arranged between the first control substrate and the second control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution.

Abstract: An electrophoresis display with micro tenon includes a control substrate having a first face and a second face, a driving circuit layer and a control electrode layer sequentially arranged on the second face, an opposite substrate having a third face opposite to the second face and a fourth face, a micro partition structure formed between the second face and the third face. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The electrophoresis display further includes a plurality of micro tenons. Each of the micro tenons is corresponding to a face of the micro partition structure and embedded into one of the chambers.

Abstract: An alloy material of polycarbonate-polyethylene terephthalate includes the following components: a polycarbonate, a polyethylene terephthalate, a transesterification inhibitor, and a compatibilizer.

Abstract: A memory device includes: a first array of memory cells; a second array of tracking cells, the second array being configured to emulate the first array; a first word line coupled to corresponding ones of the memory cells in a corresponding one of rows of the first array and to the tracking cells; a second word line configured to emulate the first word line; a first adjust circuit coupled to the first word line; a second adjust circuit coupled to the second word line; and an adjust-timing circuit coupled to the second adjust circuit.

Abstract: An electrophoresis display includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The viewing face of the electrophoresis display is on the first face of the control substrate.

Abstract: An electrophoresis display with high aperture ratio includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The driving circuit layer includes a plurality of thin film transistors (TFT), a plurality of gate lines, and plurality of data lines. Each of the gate line is connected to the gates of the TFTs and each of the data lines is connected to the sources or the drains of the TFTs. The area of a semiconductor part of the TFT is at least partially overlapped with the area of one of the gate lines or the area of one of the date lines along a projection direction.

Abstract: An electrophoresis display with high aperture ratio includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The driving circuit layer includes a plurality of thin film transistors (TFT), a plurality of gate lines, and plurality of data lines. Each of the gate line is connected to the gates of the TFTs and each of the data lines is connected to the sources or the drains of the TFTs. The sum of the data line width and the gate line width is not larger than 10 ?m. The aperture ratio of the electrophoresis display, viewed from the first face of the control substrate and toward a display area of the electrophoresis display, is not less than 80%.

Abstract: An electrophoresis display with gapped micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. Two adjacent partition walls have a gap therebetween and used as yielding space when the electrophoresis display is bent. The area of the gap is not larger than 50% of the area of the partition wall. Or the length of the gap is not longer than 50% of the length of the partition wall.

Abstract: In a method of fabricating an electronic device, a first nMOS device structure and a second nMOS device structure are formed. Each nMOS device structure includes a gate oxide disposed on a p-type base material and a gate disposed on the gate oxide. N-type dopant implantation is performed to form source and drain regions in the p-type substate of the first nMOS device structure and source and drain regions in the p-type substate of the second nMOS device structure, and to further dope the gate of the first nMOS device structure n-type to form a first nMOS device with the gate doped n-type. P-type dopant implantation is performed to dope the gate of the second nMOS device structure p-type to form the second nMOS device structure with the gate anti-doped p-type.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a first transistor. The first transistor includes a first gate structure wrapping around a plurality of first nanostructures disposed over a substrate, a first source/drain feature electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer, and a first semiconductor layer disposed between the substrate and the first source/drain feature, wherein the first source/drain feature is in direct contact with a top surface of the first semiconductor layer.

Abstract: A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.