Patents by Inventor Chia Cheng Chin
Chia Cheng Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948796Abstract: One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {100} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {110} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.Type: GrantFiled: June 10, 2020Date of Patent: April 2, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Yi-Chiau Huang, Chen-Ying Wu, Abhishek Dube, Chia Cheng Chin, Saurabh Chopra
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Publication number: 20240018658Abstract: The present disclosure relates to flow guide structures and heat shield structures, and related methods, for deposition uniformity and process adjustability. In one implementation, an apparatus for substrate processing includes a chamber body that includes a processing volume. The apparatus includes one or more heat sources. The apparatus includes a flow guide structure positioned in the processing volume. The flow guide structure includes one or more first flow dividers that divide the processing volume into a plurality of flow levels, and one or more second flow dividers oriented to intersect the one or more first flow dividers and divide each flow level of the plurality of flow levels into a plurality of flow sections. The flow guide structure includes one or more third flow dividers oriented to intersect the one or more second flow dividers and divide the plurality of flow sections into a plurality of flow zones.Type: ApplicationFiled: December 20, 2022Publication date: January 18, 2024Inventors: Zuoming ZHU, Ala MORADIAN, Shu-Kwan LAU, John TOLLE, Manjunath SUBBANNA, Martin Jeffrey SALINAS, Chia Cheng CHIN, Thomas KIRSCHENHEITER, Saurabh CHOPRA
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Publication number: 20230230859Abstract: A batch processing chamber and a process kit for use therein are provided. The process kit includes an outer liner having an upper outer liner and a lower outer liner, an inner liner, and a top plate and a bottom plate attached to an inner surface of the inner liner. The top plate and the bottom plate form an enclosure together with the inner liner, and a cassette is disposed within the enclosure. The cassette including shelves configured to retain a plurality of substrates thereon. The inner liner has inlet openings disposed on an injection side of the inner liner and configured to be in fluid communication with a gas injection assembly of a processing chamber, and outlet openings disposed on an exhaust side of the inner liner and configured to be in fluid communication with a gas exhaust assembly of the processing chamber. The inner surfaces of the enclosure comprise material configured to cause black-body radiation within the enclosure.Type: ApplicationFiled: July 12, 2021Publication date: July 20, 2023Inventors: Adel George TANNOUS, Schubert S. CHU, Shu-Kwan LAU, Kartik Bhupendra SHAH, Zuoming ZHU, Ala MORADIAN, Surajit KUMAR, Srinivasa RANGAPPA, Chia Cheng CHIN, Vishwas Kumar PANDEY
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Publication number: 20220319844Abstract: Generally, examples described herein relate to methods and semiconductor processing systems for anisotropically epitaxially growing a material on a silicon germanium (SiGe) surface. In an example, a surface of silicon germanium is formed on a substrate. Epitaxial silicon germanium is epitaxially grown on the surface of silicon germanium. A first growth rate of the epitaxial silicon germanium is in a first direction perpendicular to the surface of silicon germanium, and a second growth rate of the epitaxial silicon germanium is in a second direction perpendicular to the first direction. The first growth rate is at least 5 times greater than the second growth rate.Type: ApplicationFiled: May 7, 2020Publication date: October 6, 2022Inventors: Chia Cheng CHIN, Abhishek DUBE, Yi-Chiau HUANG, Saurabh CHOPRA
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Publication number: 20220310390Abstract: One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {100} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {110} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.Type: ApplicationFiled: June 10, 2020Publication date: September 29, 2022Inventors: Yi-Chiau HUANG, Chen-Ying WU, Abhishek DUBE, Chia Cheng CHIN, Saurabh CHOPRA
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Publication number: 20220254634Abstract: A method and apparatus for providing uniform heating of substrates disposed within a processing chamber is provided. The apparatus includes one or more heating coils disposed in the processing chamber. The one or more heating coils are electrically coupled to a power source using heater rods. The heater rods are coupled to a socket on a distal end opposite the connection to the heating coils. The socket includes a feedthrough and a cooling plate configured to remove contaminants, such as methane, from the area surrounding the heater rod.Type: ApplicationFiled: January 20, 2022Publication date: August 11, 2022Inventors: Brian Hayes BURROWS, Ala MORADIAN, Zuoming ZHU, Chia Cheng CHIN
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Publication number: 20220172989Abstract: Processing methods comprise forming a gap fill layer comprising tungsten or molybdenum by exposing a substrate surface having at least one feature thereon sequentially to a metal precursor and a reducing agent comprising hydrogen to form the gap fill layer in the feature, wherein there is not a nucleation layer between the substrate surface and the gap fill layer.Type: ApplicationFiled: February 15, 2022Publication date: June 2, 2022Applicant: Applied Materials, Inc.Inventors: Yihong Chen, Kelvin Chan, Xinliang Lu, Srinivas Gandikota, Yong Wu, Susmit Singha Roy, Chia Cheng Chin
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Patent number: 11289374Abstract: Processing methods comprise forming a gap fill layer comprising tungsten or molybdenum by exposing a substrate surface having at least one feature thereon sequentially to a metal precursor and a reducing agent comprising hydrogen to form the gap fill layer in the feature, wherein there is not a nucleation layer between the substrate surface and the gap fill layer.Type: GrantFiled: November 29, 2017Date of Patent: March 29, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Yihong Chen, Kelvin Chan, Xinliang Lu, Srinivas Gandikota, Yong Wu, Susmit Singha Roy, Chia Cheng Chin
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Patent number: 10854511Abstract: Methods for forming 3D-NAND devices comprising recessing a poly-Si layer to a depth below a spaced oxide layer. A liner is formed on the spaced oxide layer and not on the recessed poly-Si layer. A metal layer is deposited in the gaps on the liner to form wordlines.Type: GrantFiled: June 5, 2018Date of Patent: December 1, 2020Assignee: Applied Materials, Inc.Inventors: Yihong Chen, Yong Wu, Chia Cheng Chin, Xinliang Lu, Srinivas Gandikota, Ziqing Duan, Abhijit Basu Mallick
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Patent number: 10854461Abstract: Methods for depositing a metal film without the use of a barrier layer are disclosed. Some embodiments comprise forming an amorphous nucleation layer comprising one or more of silicon or boron and forming a metal layer on the nucleation layer.Type: GrantFiled: September 30, 2019Date of Patent: December 1, 2020Assignee: Applied Materials, Inc.Inventors: Yihong Chen, Yong Wu, Chia Cheng Chin, Srinivas Gandikota, Kelvin Chan
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Publication number: 20200027738Abstract: Methods for depositing a metal film without the use of a barrier layer are disclosed. Some embodiments comprise forming an amorphous nucleation layer comprising one or more of silicon or boron and forming a metal layer on the nucleation layer.Type: ApplicationFiled: September 30, 2019Publication date: January 23, 2020Inventors: Yihong Chen, Yong Wu, Chia Cheng Chin, Srinivas Gandikota
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Publication number: 20190371662Abstract: Processing methods comprise forming a gap fill layer comprising tungsten or molybdenum by exposing a substrate surface having at least one feature thereon sequentially to a metal precursor and a reducing agent comprising hydrogen to form the gap fill layer in the feature, wherein there is not a nucleation layer between the substrate surface and the gap fill layer.Type: ApplicationFiled: November 29, 2017Publication date: December 5, 2019Inventors: Yihong Chen, Kelvin Chan, Xinliang Lu, Srinivas Gandikota, Yong Wu, Susmit Singha Roy, Chia Cheng Chin
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Patent number: 10468263Abstract: Methods for depositing a metal film without the use of a barrier layer are disclosed. Some embodiments comprise forming an amorphous nucleation layer comprising one or more of silicon or boron and forming a metal layer on the nucleation layer.Type: GrantFiled: April 24, 2018Date of Patent: November 5, 2019Assignee: Applied Materials, Inc.Inventors: Yihong Chen, Yong Wu, Chia Cheng Chin, Srinivas Gandikota
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Publication number: 20180350606Abstract: Methods for forming 3D-NAND devices comprising recessing a poly-Si layer to a depth below a spaced oxide layer. A liner is formed on the spaced oxide layer and not on the recessed poly-Si layer. A metal layer is deposited in the gaps on the liner to form wordlines.Type: ApplicationFiled: June 5, 2018Publication date: December 6, 2018Inventors: Yihong Chen, Yong Wu, Chia Cheng Chin, Xinliang Lu, Srinivas Gandikota, Ziqing Duan, Abhijit Basu Mallick
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Publication number: 20180247821Abstract: Methods for depositing a metal film without the use of a barrier layer are disclosed. Some embodiments comprise forming an amorphous nucleation layer comprising one or more of silicon or boron and forming a metal layer on the nucleation layer.Type: ApplicationFiled: April 24, 2018Publication date: August 30, 2018Inventors: Yihong Chen, Yong Wu, Chia Cheng Chin, Srinivas Gandikota