Patents by Inventor Chia Cheng HO

Chia Cheng HO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210055646
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Inventors: Chien-Cheng CHEN, Chia-Jen CHEN, Hsin-Chang LEE, Shih-Ming CHANG, Tran-Hui SHEN, Yen-Cheng HO, Chen-Shao HSU
  • Publication number: 20210057290
    Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Shiang LIN, Chia-Cheng HO, Chun-Chieh LU, Cheng-Yi PENG, Chih-Sheng CHANG
  • Patent number: 10872893
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate and forming a first gate structure over a first portion of the fin structure. A first nitride layer is formed over a second portion of the fin structure. The first nitride layer is exposed to ultraviolet radiation. Source/drain regions are formed at the second portion of the fin structure.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lin Yang, Chia-Cheng Ho, Chih Chieh Yeh, Cheng-Yi Peng, Tsung-Lin Lee
  • Patent number: 10861946
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate disposed over a drift region. A first gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an outer sidewall of the first gate electrode to the drain region. The etch stop layer overlies the drift region disposed between the source region and the drain region. A field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate overlies the drift region. A top surface of the field plate is aligned with a top surface of the first gate electrode and a bottom surface of the field plate is vertically above a bottom surface of the first gate electrode. The field plate and first gate electrode respectively include metal materials.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
  • Publication number: 20200373395
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate disposed over a drift region. A first gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an outer sidewall of the first gate electrode to the drain region. The etch stop layer overlies the drift region disposed between the source region and the drain region. A field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate overlies the drift region. A top surface of the field plate is aligned with a top surface of the first gate electrode and a bottom surface of the field plate is vertically above a bottom surface of the first gate electrode. The field plate and first gate electrode respectively include metal materials.
    Type: Application
    Filed: May 21, 2019
    Publication date: November 26, 2020
    Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
  • Patent number: 10818562
    Abstract: A method for testing a semiconductor structure includes forming a dielectric layer over a test region of a substrate. A cap layer is formed over the dielectric layer. The dielectric layer and the cap layer are annealed. The annealed cap layer is removed. A ferroelectricity of the annealed dielectric layer is in-line tested.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Shiang Lin, Chia-Cheng Ho, Chun-Chieh Lu, Cheng-Yi Peng, Chih-Sheng Chang
  • Patent number: 10816892
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Cheng Chen, Chia-Jen Chen, Hsin-Chang Lee, Shih-Ming Chang, Tran-Hui Shen, Yen-CHeng Ho, Chen-Shao Hsu
  • Patent number: 10797174
    Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Tai Chang, Tung Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
  • Publication number: 20200273996
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
  • Publication number: 20200273997
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
  • Patent number: 10707347
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Yuan, Chia-Cheng Ho, Tzu-Chung Wang, Tung Ying Lee, Jin Cai, Ming-Shiang Lin
  • Publication number: 20200132453
    Abstract: Pressure assisted positioning method and device thereof are disclosed in the present invention. The pressure assisted positioning device is exerted for positioning a target under the circumstance of altitude change since the target enters a specific region. The pressure assisted positioning method includes the following steps. First, confirming the entrance of the specific region of the target and detecting a plurality of pressure data. Then, calculating a pressure variation between the two selected pressure data. At last, comparing the pressure variation to a threshold. An altitude change within the specific region is confirmed as the pressure variation is greater than the threshold. On the other hand, as the pressure variation is greater than the threshold, it refers to no altitude change within the specific region.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 30, 2020
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Ping-Fan Ho, Chia-Cheng Wang, Jyh-Cheng Chen
  • Publication number: 20200126988
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate and forming a first gate structure over a first portion of the fin structure. A first nitride layer is formed over a second portion of the fin structure. The first nitride layer is exposed to ultraviolet radiation. Source/drain regions are formed at the second portion of the fin structure.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 23, 2020
    Inventors: Yu-Lin YANG, Chia-Cheng HO, Chih Chieh YEH, Cheng-Yi PENG, Tsung-Lin LEE
  • Publication number: 20200127138
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Application
    Filed: January 23, 2019
    Publication date: April 23, 2020
    Inventors: Feng Yuan, Chia-Cheng Ho, Tzu-Chung Wang, Tung Ying Lee, Jin Cai, Ming-Shiang Lin
  • Publication number: 20200083446
    Abstract: Provided is a method of fabricating a resistive memory including forming a first electrode and a second electrode opposite to each other; forming a variable resistance layer between the first electrode and the second electrode; forming an oxygen exchange layer between the variable resistance layer and the second electrode; and forming a protection layer at least covering sidewalls of the oxygen exchange layer.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Ting-Ying Shen, Chia-Hua Ho, Chih-Cheng Fu, Frederick Chen
  • Publication number: 20200058784
    Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 20, 2020
    Inventors: Kai-Tai CHANG, Tung Ying LEE, Wei-Sheng YUN, Tzu-Chung WANG, Chia-Cheng HO, Ming-Shiang LIN, Tzu-Chiang CHEN
  • Publication number: 20200058763
    Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.
    Type: Application
    Filed: September 5, 2019
    Publication date: February 20, 2020
    Inventors: Kai-Tai CHANG, Tung Ying LEE, Wei-Sheng YUN, Tzu-Chung WANG, Chia-Cheng HO, Ming-Shiang LIN, Tzu-Chiang CHEN
  • Patent number: 10522755
    Abstract: Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: December 31, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Ting-Ying Shen, Chia-Hua Ho, Chih-Cheng Fu, Frederick Chen
  • Patent number: 10505040
    Abstract: A method for manufacturing a semiconductor device comprises forming a first fin and a second fin on a first active region and a second active region of a semiconductor substrate, respectively. A first dummy gate is formed over the first fin and a second dummy gate is formed over the second fin, wherein the first dummy gate has a first gate width along a lengthwise direction of the first fin, the second dummy gate has a second gate width along the lengthwise direction of the second fin, the first gate width is different from the second gate width. At least one of the first dummy gate and the second dummy gate is removed. A ferroelectric layer is then formed over the semiconductor substrate, in which the first dummy gate and/or the second dummy gate is removed. At least one metal gate electrode is formed on the ferroelectric layer.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Ho, Ming-Shiang Lin, Cheng-Yi Peng, Chun-Chieh Lu, Chih-Sheng Chang, Carlos H. Diaz
  • Patent number: 10483235
    Abstract: A method for fabricating a stacked electronic device is provided. A first three-dimensional (3D) printing is performed to form a first insulating layer and a plurality of first redistribution layers (RDLs) on a first substrate. A second 3D printing is performed to form a second substrate and a plurality of through-substrate vias (TSVs) on the first insulating layer, in which the plurality of TSVs is electrically connected to the plurality of first RDLs. A third 3D printing is performed to form a second insulating layer and a plurality of second RDLs on the second substrate, in which the plurality of second RDLs is electrically connected to the plurality of TSVs. A plurality of contacts of a third substrate is bonded to the plurality of second RDLs, so that the substrate is mounted onto the second insulating layer. The disclosure also provides a stacked electronic device formed by such a method.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: November 19, 2019
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Yu-Cheng Chiao, Tung-Yi Chan, Chen-Hsi Lin, Chia Hua Ho, Meng-Chang Chan, Hsin-Hung Chou