Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.

Abstract: A method for adjusting a projection parameter and a projection system are disclosed. In the projection system, a processor is configured to drive multiple projectors to project multiple projection images respectively and obtain a full projection range through calculation, select a target area from at least one overlapping area included in the full projection range and obtain a target projection parameter value of the target area, obtain multiple intersection points of the overlapping area on a boundary of the full projection range, define connecting lines between a center point of the target area and the intersection points as dividing lines to divide the full projection range into multiple sub-areas, respectively adjust a projection parameter value of each of the sub-areas according to the target projection parameter value of the target area, and perform projection through the corresponding projector based on the adjusted projection parameter value of each of the sub-areas.

Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.

Abstract: A method for adjusting a projection boundary and a projection system are provided. Multiple imaging apparatuses corresponding to multiple projection apparatuses are driven, and each imaging apparatus obtains a corresponding captured image by capturing projected image projected by corresponding one projection apparatus and surrounding area of the projected image. All captured images are displayed on a display, and a main bounding box corresponding to each projected image and a reference bounding box corresponding to the surrounding area are displayed on each captured image. The main bounding box of each captured image is independently adjusted relative to the reference bounding box to obtain an adjusted main bounding box. A full image boundary is calculated based on the respective adjusted main bounding boxes. The projection apparatuses are driven to project an adjusted full image based on the full image boundary.

Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

Abstract: A pharmaceutical composition containing a mixed polymeric micelle and a drug enclosed in the micelle, in which the mixed polymeric micelle, 1 to 1000 nm in size, includes an amphiphilic block copolymer and a lipopolymer. Also disclosed are preparation of the pharmaceutical composition and use thereof for treating cancer.

Abstract: A sealing article includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: A method of making a sealing article that includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.

Abstract: A low-melting-point alloy composite material and a composite material structure are provided. The low-melting-point alloy composite material includes 48 to 54 wt. % In, 30 to 36 wt. % Bi, 14 to 21 wt. % Sn, and at least one selected from 0.1 to 0.3 wt. % carbon material and 0.05 to 0.1 wt. % boron nitride (BN). The composite material structure includes a metal layer, a low-melting-point alloy composite material layer, and an interface material layer, wherein the material of the low-melting-point alloy composite material layer is the above low-melting-point alloy composite material, and the interface material layer is formed between the metal layer and the low-melting-point alloy composite material layers.

Abstract: An anti-corrosion structure and a fuel cell employing the same are provided. The anti-corrosion structure includes an aluminum layer, a first anti-corrosion layer, and an intermediate layer disposed between the aluminum layer and the first anti-corrosion layer. In particular, the first anti-corrosion layer can be a nickel-tin-containing alloy layer, and the intermediate layer can be a nickel-tin-aluminum-containing alloy layer.

Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming an antenna structure in contact with one side of a circuit structure of a packaging substrate, and disposing an electronic component on the other side of the circuit structure. As such, the antenna structure is integrated with the packaging substrate, thereby reducing the thickness of the electronic package and improving the efficiency of the antenna structure.

Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming an antenna structure in contact with one side of a circuit structure of a packaging substrate, and disposing an electronic component on the other side of the circuit structure. As such, the antenna structure is integrated with the packaging substrate, thereby reducing the thickness of the electronic package and improving the efficiency of the antenna structure.

Abstract: An anti-corrosion structure and a fuel cell employing the same are provided. The anti-corrosion structure includes an aluminum layer, a first anti-corrosion layer, and an intermediate layer disposed between the aluminum layer and the first anti-corrosion layer. In particular, the first anti-corrosion layer can be a nickel-tin-containing alloy layer, and the intermediate layer can be a nickel-tin-aluminum-containing alloy layer.

Abstract: A display panel includes a first substrate, a second substrate, a seal, a display medium and a plurality of the first supporting structures. The second substrate is opposite to the first substrate in a top-bottom manner. The seal, the display medium and the plurality of the first supporting structures are disposed between the first substrate and the second substrate. The seal has a frame-like shape to define a set area and the display medium and the plurality of the first supporting structures are located within the set area. Besides, each first supporting structure abuts against the first substrate and the second substrate and has a supporting area, wherein a ratio of the supporting area of the first supporting structures to the set area is 0.03% to 0.08%.

Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

Abstract: The method and system for reminding readers of fatigue in reading while using electronic devices are revealed. First use a reading speed calculation module to detect user's reading speed within a period of time when the user is using an electronic with a display to read. The reading speed is related to pages being turned or the amount of words being read. Then a fatigue-in-reading reminder module is activated by the reading speed calculation module when the user's reading speed falls within a specific range so as to remind the user by pop-up windows, sounds, flash light or vibration at the proper time and provide the user certain corresponding measures he/she should take. Thereby there is no need to use additional equipment for preventing users from becoming more fatigue and healthy vision is accomplished at lower cost with higher efficiency.

Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

Abstract: The method and system for reminding readers of fatigue in reading while using electronic devices are revealed. First use a reading speed calculation module to detect user's reading speed within a period of time when the user is using an electronic with a display to read. The reading speed is related to pages being turned or the amount of words being read. Then a fatigue-in-reading reminder module is activated by the reading speed calculation module when the user's reading speed falls within a specific range so as to remind the user by pop-up windows, sounds, flash light or vibration at the proper time and provide the user certain corresponding measures he/she should take. Thereby there is no need to use additional equipment for preventing users from becoming more fatigue and healthy vision is accomplished at lower cost with higher efficiency.

Abstract: A thermoelectric alloy material and thermoelectric element are provided, wherein the thermoelectric alloy material includes a Half-Heusler (HH) composition as matrix. The thermoelectric alloy material is represented by following formula (I): (Zra1Hfb1)x(Fec1Cod1)y(Sbe1Snf1)z ??(I) In the formula (I), 0<a1<1, 0<b1<1, 0<c1<1, 0<d1<1, 0<e1<1, 0<f1<1, a1+b1=1, c1+d1=1, e1+f1=1, c1?f1, and 0.25?x, y, z?0.35.