Abstract: A violation checking method includes generating a violation log report for a design, classifying violation logs in the violation log report into high-risk logs and low-risk logs by a machine learning model, reviewing the high-risk logs, and modifying the design if at least one bug is identified in the high-risk logs.

Abstract: An electronic device includes a substrate, a driving element, a first insulating layer, a pixel electrode layer, and a common electrode layer. The driving element is disposed on the substrate. The first insulating layer is disposed on the driving element. The pixel electrode layer is disposed on the first insulating layer. The first insulating layer comprises a hole, and the pixel electrode layer is electrically connected to the driving element through the hole. The common electrode layer is disposed on the pixel electrode layer. The common electrode layer comprises a slit, and the slit has an edge, and the edge is disposed in the hole.

Abstract: The present invention relates to a method for preparing a modified stem cell, including the following steps: a cell culture step: culturing stem cells in a first culture medium of a culture dish at a predetermined cell density, and removing the first culture medium after a first culture time to obtain a first cell intermediate; an activity stimulation step: preserving the first cell intermediate in a freezing container having a cell cryopreservation solution, and performing a constant temperature stimulation treatment or a variable temperature stimulation treatment for at least more than 1 day; and a product collection step: after completing the activity stimulation step, placing the freezing container in an environment at a thawing temperature for thawing, and then removing the cell cryopreservation solution to obtain the modified stem cell. The modified stem cell can release at least one or more of IL-4, IL-5, IL-13, G-CSF, Fractalkine, and EGF.

Abstract: A variable aperture module includes a blade assembly, a positioning element, a driving part and pressing structures. The blade assembly includes movable blades disposed around an optical axis to form a light passable hole with an adjustable size. Each movable blade has a positioning hole and a movement hole adjacent thereto. The positioning element includes positioning structures disposed respectively corresponding to the positioning holes. The driving part includes a rotation element disposed corresponding to the movement holes and is rotatable with respect to the positioning element. The pressing structures are disposed respectively corresponding to the movable blades. Each pressing structure is at least disposed into at least one of the positioning hole and the movement hole of the corresponding movable blade. Each pressing structure at least presses against at least one of the corresponding one positioning structure and the rotation element.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: A display device includes a display panel. The display panel has a functional display area. The functional display area includes a plurality of display pixels and a plurality of light transmitting regions. The plurality of display pixels are around by the plurality of the light transmitting regions. A boundary between one of the plurality of display pixels and one of the plurality of light transmitting regions comprises an arc segment.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: An artificial intelligence (AI)-based constrained random verification (CRV) method for a design under test (DUT) includes: receiving a series of constraints; obtaining a limited constraint range according to the series of constraints; generating a series of stimuli according to the limited constraint range; and verifying the DUT by the series of stimuli; wherein at least one of the step of obtaining the limited constraint range according to the series of constraints and the step of generating the series of stimuli according to the limited constraint range employs an AI algorithm.

Abstract: A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.