Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes channel structures vertically separated from each other and a gate structure wrapping around the channel structures. The semiconductor structure further includes a first porous layer formed over a first sidewall of the gate structure under the channel structures and a source/drain structure attached to the channel structures. In addition, the source/drain structure is laterally separated from the first porous layer by a first air gap.

Abstract: A method includes following steps. A semiconductor fin is formed on a substrate. A source/drain recess is formed in the semiconductor fin. A first isolation sidewall dielectric and a second isolation sidewall dielectric are formed lining opposite sidewalls of the source/drain recess. An epitaxial layer is formed in the source/drain recess. The epitaxial layer is recessed such that a top surface of the epitaxial layer is lower than top surfaces of the first and second isolation sidewall dielectrics. An epitaxial source/drain region is formed on the recessed epitaxial layer. A gate structure is formed adjacent the epitaxial source/drain region.

Abstract: A device includes a stack of first nanostructures; a first insulating layer adjacent to the stack of first nanostructures; a first source/drain region over the first insulating layer, wherein the first source/drain region includes a first semiconductor layer extending continuously over the sidewalls of the first nanostructures, wherein the first semiconductor layer is a first semiconductor material and a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is a second semiconductor material different from the first semiconductor material.

Abstract: A device includes a stack of first nanostructures; a first insulating layer adjacent to the stack of first nanostructures; and a first source/drain region over the first insulating layer, wherein the first source/drain region includes: first semiconductor layers, wherein each first semiconductor layer covers a sidewall of a respective first nanostructure, wherein the first semiconductor layers includes a first semiconductor material; second semiconductor layers, wherein each second semiconductor layer covers a sidewall of a respective first semiconductor layer, wherein the second semiconductor layers includes a second semiconductor material different from the first semiconductor material; and a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer is a third semiconductor material different from the first semiconductor material and different from the second semiconductor material.

Abstract: A semiconductor structure includes a plurality of nanosheets, a gate structure, an S/D structure, a stepped structure, and a sidewall spacer. The plurality of nanosheets is disposed over a substrate, wherein the substrate extends along a first direction, and the nanosheets are arranged along a second direction substantially perpendicular to the first direction. The gate structure is disposed over the substrate, wherein the gate structure is disposed between and surrounding the nanosheets. The S/D structure is disposed adjacent to the gate structure and the plurality of nanosheets. The stepped structure is disposed below the S/D structure, wherein the stepped structure overlaps at least one of the nanosheets along the first direction. The sidewall spacer is disposed between the stepped structure and the at least one of the nanosheets. A method of manufacturing the semiconductor structure is also provided.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures formed over a substrate along a first direction, and a gate structure formed over the nanostructures along a second direction. The semiconductor structure includes an S/D structure formed adjacent to the gate structure, and a plurality of inner spacer layers between the gate structure and the S/D structure. The semiconductor structure includes a hard mask layer formed on the inner spacer layers, and a top surface of the hard mask layer is higher than a top surface of the S/D structure.

Abstract: A variable aperture module includes a blade assembly, a positioning element, a driving part and pressing structures. The blade assembly includes movable blades disposed around an optical axis to form a light passable hole with an adjustable size. Each movable blade has a positioning hole and a movement hole adjacent thereto. The positioning element includes positioning structures disposed respectively corresponding to the positioning holes. The driving part includes a rotation element disposed corresponding to the movement holes and is rotatable with respect to the positioning element. The pressing structures are disposed respectively corresponding to the movable blades. Each pressing structure is at least disposed into at least one of the positioning hole and the movement hole of the corresponding movable blade. Each pressing structure at least presses against at least one of the corresponding one positioning structure and the rotation element.

Abstract: A semiconductor device includes two source/drain regions, two isolation elements, a channel feature, at least one semiconductor layer and a gate feature. The source/drain regions are spaced apart from each other, and are respectively disposed above the isolation elements. The channel feature includes at least one effective channel layer and at least one dummy channel layer that are spaced apart from each other. Each of the at least one effective channel layer extends between the source/drain regions. Each of the at least one dummy channel layer extends between the isolation elements. The at least one semiconductor layer at least covers a lower surface of a bottommost one of the at least one dummy channel layer. The gate feature is disposed around the at least one effective channel layer, such that two opposite surfaces of each of the at least one effective channel layer are adjacent to the gate feature.

Abstract: A semiconductor device includes a substrate, an active structure, a first dielectric layer and a second dielectric layer. The active structure is formed on the substrate and includes an active channel sheet, wherein the active channel sheet has a first lateral surface. The first dielectric layer is formed above the active structure and has a recess, wherein the recess is recessed with respect to the first lateral surface of the active channel sheet. The second dielectric layer is formed within the recess and has a dielectric constant, wherein the dielectric constant is less than 3.9.

Abstract: An imaging lens assembly module includes an imaging lens assembly and a variable aperture module. The imaging lens assembly has an optical axis. The variable aperture module includes a light blocking sheet set, a fixed element, a movable element, and an annular light blocking portion. The light blocking sheet set includes at least two light blocking sheets, wherein the at least two light blocking sheets are mutually stacked along a circumferential direction surrounding the optical axis to form a variable aperture opening. The fixed element has a sidewall structure. The annular light blocking portion surrounds the optical axis to form a fixed aperture opening.

Abstract: A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a first transistor. The first transistor includes a first gate structure wrapping around a plurality of first nanostructures disposed over a substrate, a first source/drain feature electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer, and a first semiconductor layer disposed between the substrate and the first source/drain feature, wherein the first source/drain feature is in direct contact with a top surface of the first semiconductor layer.

Abstract: A device includes: a substrate; a stack of semiconductor channels on the substrate; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; and a hybrid structure between the source/drain region and the substrate. The hybrid structure includes: a first semiconductor layer under the source/drain region; and an isolation region extending vertically from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer.

Abstract: A semiconductor structure includes an isolation structure in a substrate, a metal gate structure over the substrate and a portion of the isolation structure, a spacer at sidewalls of the metal gate structure, epitaxial source/drain structure at two sides of the metal gate structure, and a protection layer over the isolation structure. The protection layer and the spacer include a same material.

Abstract: An imaging lens module includes an imaging lens, an adjustable aperture module, a first spacer and a second spacer. The adjustable aperture module is disposed between an object-side lens group and an image-side lens group of the imaging lens and comprises a blade assembly, fixed shafts, a movable component and a driving mechanism. The blade assembly includes at least two light-blocking blades forming a light pass aperture. The driving mechanism is to rotate the movable component in a circumferential direction, allowing the blade assembly to move relative to the fixed shafts for varying an aperture size of the light pass aperture. The fixed shafts are disposed on the first spacer. The second spacer and the first spacer together form an inner space in which the adjustable aperture module is accommodated. The second spacer receives and is in physical contact with the object-side lens group.

Abstract: A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

Abstract: A method for forming a semiconductor device structure includes forming a fin structure, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack wrapped around the fin structure and forming a spacer layer extending along sidewalls of the fin structure and the gate stack. The method further includes partially removing the fin structure and the spacer layer to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. A remaining portion of the spacer layer forms a gate spacer. In addition, the method includes forming an inner spacer layer along a sidewall and a bottom of the recess and partially removing the inner spacer layer using an isotropic etching process. Remaining portions of the inner spacer layers form multiple inner spacers. The method includes forming an epitaxial structure in the recess.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a polysilicon structure on a substrate, depositing a first spacer layer on the polysilicon structure, depositing a second spacer layer on the first spacer layer, forming a S/D region on the substrate, removing the second spacer layer, depositing a third spacer layer on the first spacer layer and on the S/D region, depositing an ESL on the third spacer layer, depositing an ILD layer on the etch stop layer, and replacing the polysilicon structure with a gate structure surrounding the nanostructured layer.

Abstract: A variable aperture module includes a blade assembly, a positioning element, a driving part and pressing structures. The blade assembly includes movable blades disposed around an optical axis to form a light passable hole with an adjustable size. Each movable blade has a positioning hole and a movement hole adjacent thereto. The positioning element includes positioning structures disposed respectively corresponding to the positioning holes. The driving part includes a rotation element disposed corresponding to the movement holes and is rotatable with respect to the positioning element. The pressing structures are disposed respectively corresponding to the movable blades. Each pressing structure is at least disposed into at least one of the positioning hole and the movement hole of the corresponding movable blade. Each pressing structure at least presses against at least one of the corresponding one positioning structure and the rotation element.

Abstract: A device includes: a stack of nanostructures; a gate structure that wraps around the nanostructures; an isolation region between the stack of nanostructures and another stack of nanostructures adjacent thereto along a first direction; a source/drain region that abuts at least one of the nanostructures; and a spacer layer that is on sidewalls of the gate structure and on sidewalls of the source/drain region, the spacer layer covering an area between the source/drain region and a neighboring source/drain region of another transistor along the first direction.