Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.

Abstract: An information processing method of the present disclosure includes: via one or more computer processors, receiving data relating to live sales performed by a livestreamer via live video streaming; inputting the data into a machine learning model; and based on a result generated by the machine learning model, obtaining promotional information that is useful for the livestreamer to perform the live sales.

Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.

Abstract: A respiratory function testing system includes an air transforming device, a sound reception device and an operation device. The air transforming device is configured to collect exhaled and/or inhaled air for a predetermined period and generate a wide frequency range sound signal according to the collected respired air. The wide frequency range sound signal at least contains an ultrasonic signal. The sound reception device is configured to receive and record the wide frequency range sound signal as an audio file. The operation device is in communication with the sound reception device and is configured to receive and compute the audio file to generate a respiratory function parameter. Besides, the recorded wide frequency range sound signal may be converted into a spectrogram for further applications, and the computation of the audio file can be replaced by analyzing the spectrogram. A respiratory function testing method corresponding to the respiratory function testing system is also provided.

Abstract: A method, comprising: detecting an outage of at least one functionality in a live streaming; performing an first operation toward a second user terminal; storing data of the first operation in a database of the first user terminal; and displaying an effect corresponding to the first operation during the outage. The present disclosure may store the data of operation performed by the user terminal during outage and process the operation after the outage is recovered. Therefore, the streamers and viewers may feel interested and satisfied, instead of feeling anxious, and the user experience may be enhanced.

Abstract: Aspects described herein relate to a method comprising: receiving a request to write data to a persistent storage device, the request comprising data; determining an affinity of the data; writing the request to a cache line of a cache; associating the cache line with the affinity of the data; and reporting the data as having been written to the persistent storage device.

Abstract: The present disclosure provides a process variation detection circuit and a process variation detection method. The process variation detection circuit is arranged in a chip and includes: a first ring oscillator, where a first number of auxiliary elements of a preset type are arranged between two adjacent inverters of the first ring oscillator; and a second ring oscillator, where a second number of auxiliary elements of a preset type are arranged between two adjacent inverters of the second ring oscillator, the second number is larger than the first number; wherein, a number of the inverter of the first ring oscillator is the same as a number of the inverter of the second ring oscillator; a type and a size of a transistor of the first ring oscillator are the same as a type and a size of a transistor of the second ring oscillator.

Abstract: Embodiments relate to a data storage circuit and a control method thereof, and a storage apparatus. The data storage circuit includes a first storage array and a sense amplifier array, the first storage array is positioned on a side of the sense amplifier array, and the sense amplifier array is electrically connected to a main bit line. The first storage array includes a plurality of first sub storage arrays, each of the plurality of first sub storage arrays includes a plurality of first sub bit lines and a plurality of first selector switches, each of the plurality of first sub bit lines is electrically connected to the main bit line via one of the plurality of first selector switches, and the sense amplifier array is configured to amplify a signal of the main bit line.

Abstract: The present disclosure provides a process variation detection circuit and a process variation detection method. The process variation detection circuit is arranged in a chip and includes: a first ring oscillator, where a first number of auxiliary elements of a preset type are arranged between two adjacent inverters of the first ring oscillator; and a second ring oscillator, where a second number of auxiliary elements of a preset type are arranged between two adjacent inverters of the second ring oscillator, the second number is larger than the first number; wherein, a number of the inverter of the first ring oscillator is the same as a number of the inverter of the second ring oscillator; a type and a size of a transistor of the first ring oscillator are the same as a type and a size of a transistor of the second ring oscillator.

Abstract: The present disclosure provides a process corner detection circuit and a process corner detection method. The process corner detection circuit includes: M ring oscillators disposed inside a chip, M?1, where types of N-type transistors in the M ring oscillators are not exactly the same, and types of P-type transistors in the M ring oscillators are not exactly the same; transistor types of the M ring oscillators include all transistor types used in the chip; the ring oscillators include symmetric ring oscillators and asymmetric ring oscillators; types of N-type transistors and P-type transistors in the symmetric ring oscillators are the same; and types of N-type transistors and P-type transistors in the asymmetric ring oscillators are different.

Abstract: The embodiments of the present invention discloses an arrangement of bond pads on an integrated circuit chip. The integrated circuit chip includes: a first row of bond pads; and a second row of bond pads, wherein bond pads in the first row are positioned alternately with bond pads in the second row, and a short side of the bond pads in the first row and the second row is parallel to a long side of the integrated circuit chip. With this arrangement of bond pads on the integrated circuit chip, the bond pads may occupy a reduced area of a surface of the integrated circuit chip.

Abstract: The present disclosure provides a process corner detection circuit and a process corner detection method. The process corner detection circuit includes: M ring oscillators disposed inside a chip, M?1, where types of N-type transistors in the M ring oscillators are not exactly the same, and types of P-type transistors in the M ring oscillators are not exactly the same; transistor types of the M ring oscillators include all transistor types used in the chip; the ring oscillators include symmetric ring oscillators and asymmetric ring oscillators; types of N-type transistors and P-type transistors in the symmetric ring oscillators are the same; and types of N-type transistors and P-type transistors in the symmetric ring oscillators are different.

Abstract: Aspects described herein relate to a method comprising: receiving a request to write data to a persistent storage device, the request comprising data; determining an affinity of the data; writing the request to a cache line of a cache; associating the cache line with the affinity of the data; and reporting the data as having been written to the persistent storage device.

Abstract: A chip test device and a chip test method are provided. The chip test device may include a chip socket and an interface card comprising a signal synthesizer, a plurality of first interfaces and a second interface. The signal synthesizer may be configured to synthesize a plurality of low-frequency first signals output from a plurality of testers into a high-frequency second signal and transmit the second signal to the chip socket. The plurality of first interfaces may be arranged in a plurality of inputs of the signal synthesizer for connecting the testers, and the second interface may be arranged in an output of the signal synthesizer for connecting the chip socket. By synthesizing the low-frequency first signals into the high-frequency second signal, a high-frequency test may be conducted using a plurality of low-frequency testers.

Abstract: The present invention provides a test method, a tester, a load board and a test system. The test method includes: outputting, through a first input/output (I/O) port of a tester, a first test signal to a first channel of a load board, wherein the first test signal is used to generate a second test signal and a third test signal; receiving, through the first I/O port, a third feedback signal returned from the first channel, wherein the third feedback signal is generated based on a first feedback signal and a second feedback signal; and determining whether a first chip and a second chip are operating normally based on the third feedback signal. Solutions provided in the present invention are capable of increasing the number of chips that can be tested at a single time.

Abstract: A data compression circuit, a memory device and an integrated circuit (IC) test device and method are disclosed. The data compression circuit includes a data-writing circuit and a data-reading circuit. The data-writing circuit includes a first input interface, a plurality of first output interfaces and a data-writing module, and the data-reading circuit includes a plurality of second input interfaces, a second output interface and a data-reading module. The data-writing module may be configured to write out-going data into an IC, and the data-reading module may be configured to read incoming data from the IC and generate a test result based on the incoming data. In this data compression circuit, the combination of the data-writing circuit and the data-reading circuit may bring a multi-fold increase in the number of ICs that can be tested simultaneously, which substantially improves the test efficiency and reduces the cost of a test.

Abstract: The embodiments of the present invention discloses an arrangement of bond pads on an integrated circuit chip. The integrated circuit chip includes: a first row of bond pads; and a second row of bond pads, wherein bond pads in the first row are positioned alternately with bond pads in the second row, and a short side of the bond pads in the first row and the second row is parallel to a long side of the integrated circuit chip. With this arrangement of bond pads on the integrated circuit chip, the bond pads may occupy a reduced area of a surface of the integrated circuit chip.

Abstract: A wafer structure, a die fabrication method and a chip are provided. The wafer structure may include a wafer body and a test pad. The wafer body may include a dicing region and a functional region, and the test pad may be in the dicing region. The dicing region may be cut off in a subsequent process, and the test pad may only be needed in the wafer testing stage for engineering analysis and thus can be removed thereafter. The wafer structure may further comprise a switch circuit provided between the test pad and a plurality of dies. By arranging the test pad in the dicing region and connected to one of the plurality of dies, a wafer test can be accomplished with the test pad without the test pads occupying large areas of the functional regions of the wafer. Thus, a wafer's effective area can be more efficiently utilized.

Abstract: A chip test device and a chip test method are provided. The chip test device may include a chip socket and an interface card comprising a signal synthesizer, a plurality of first interfaces and a second interface. The signal synthesizer may be configured to synthesize a plurality of low-frequency first signals output from a plurality of testers into a high-frequency second signal and transmit the second signal to the chip socket. The plurality of first interfaces may be arranged in a plurality of inputs of the signal synthesizer for connecting the testers, and the second interface may be arranged in an output of the signal synthesizer for connecting the chip socket. By synthesizing the low-frequency first signals into the high-frequency second signal, a high-frequency test may be conducted using a plurality of low-frequency testers.

Abstract: The present invention provides a laser projection clock, comprising a driving device, one or a plurality of pointer light source device, and one or a plurality of grating. The driving device comprises one or a plurality of rotating shafts and power elements for driving the one or plurality of the rotating shafts to rotate at different speeds respectively. The one or plurality of pointer light source devices is configured on one side of the driving device to each output a laser beam. The one or plurality of gratings is configured on the one or a plurality of rotating shafts in a one-on-one manner in order to be rotated by the one or plurality of rotating shafts respectively. The grating has an indication pattern, and the one or plurality of laser beams are projected to a projection plane through the one or a plurality of indication patterns of the one or plurality of gratings to form one or plurality of laser indications respectively.