Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: An electronic device is provided. The electronic device includes a substrate and a plurality of units disposed on the substrate. A portion of the plurality of units includes a conductive layer and an insulating layer. The conductive layer has a first opening penetrating through the conductive layer. The insulating layer is disposed on the conductive layer and includes a second opening penetrating through the insulating layer. The first opening of the conductive layer and the second opening of the insulating layer are at least partially overlapped. Moreover, a width of the first opening of the conductive layer is greater than a width of the second opening of the insulating layer.

Abstract: This document describes methods and systems for an antenna system integrated with side-keys of an electronic device. The antenna system enables antenna integration in a metal frame using a metal support structure and fastener(s) to route antenna signals around side-key modules embedded in the frame without encountering or causing interference with the side-key modules. By using these techniques to integrate antennas on areas around the side-key modules, more antennas can be implemented on the electronic device, leading to improved capabilities supporting additional wireless standards and a better user experience in terms of improved communication quality.

Abstract: The invention provides a slot die coating apparatus and the coating method thereof. The flow path is divided into a first flow path and a second flow path by the shim group. The first flow path is utilized to coat from the middle portion of the coating nozzle and the second flow path is utilized to coat from the two sides of the coating nozzle. The height for coating of the slot die coating apparatus is adjustable, and the slurry may be exposed from the first flow path or the second flow path. Therefore, hitting the obstacle of the substrate can be avoided during coating to achieve the optimized coating.

Abstract: The invention provides a slot die coating apparatus and the coating method thereof. The flow path is divided into a first flow path and a second flow path by the shim group. The first flow path is utilized to coat from the middle portion of the coating nozzle and the second flow path is utilized to coat from the two sides of the coating nozzle. The nozzle lips at the two sides of the slot die coating apparatus are extended to close the substrate to prevent to hit the obstacle of the substrate during coating. Also, the height for coating of the slot die coating apparatus is controllable to achieve the optimized coating.

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according one embodiment of the present disclosure include a plurality of channel members disposed over a substrate, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. The source/drain feature includes a first epitaxial layer in contact with the substrate and the plurality of channel members, and a second epitaxial layer in contact with the first epitaxial layer and the plurality of inner spacer features. The first epitaxial layer and the second epitaxial layer include silicon germanium. A germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a first transistor and a second transistor arranged over a substrate. The first transistor includes first and second source/drain regions over the substrate and includes a first channel structure directly between the first and second source/drain regions. A first gate electrode is arranged over the first channel structure and is between first and second air spacer structures. The second transistor includes third and fourth source/drain regions over the substrate and includes a second channel structure directly between the third and fourth source/drain regions. A second gate electrode is arranged over the second channel structure and is between third and fourth air spacer structures. The integrated chip further includes a high-k dielectric spacer structure over a low-k dielectric fin structure between the first and second channel structures to separate the first and second gate electrodes.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a first transistor and a second transistor arranged over a substrate. The first transistor includes first and second source/drain regions over the substrate and includes a first channel structure directly between the first and second source/drain regions. A first gate electrode is arranged over the first channel structure and is between first and second air spacer structures. The second transistor includes third and fourth source/drain regions over the substrate and includes a second channel structure directly between the third and fourth source/drain regions. A second gate electrode is arranged over the second channel structure and is between third and fourth air spacer structures. The integrated chip further includes a high-k dielectric spacer structure over a low-k dielectric fin structure between the first and second channel structures to separate the first and second gate electrodes.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A media streaming device includes a power manager, a stream processor, and a voltage detector. The power manager receives a power signal from the media playback device to supply power to the stream processor. The stream processor provides media stream to the media playback device for playback. The voltage detector is electrically coupled to the stream processor and captures at least a part of the power supply current to the stream processor. The stream processor is configured to determine whether the power supply voltage remains stable. When the supply voltage remains stable, the stream processor operates in a first mode to provide media stream. When the power supply voltage is unstable, the stream processor operates in a second mode to provide media stream, and the power consumption of the stream processor in the second mode is lower than the power consumption in the first mode.

Abstract: A design method of a photomask structure including the following steps is provided. A first layout pattern is provided. An assist pattern is added aside the first layout pattern. An optical proximity correction (OPC) is performed to convert the first layout pattern into a second layout pattern, wherein the assist pattern has an adjacent portion adjacent to the second layout pattern, a first distance between the adjacent portion and the second layout pattern is less than a safety distance, and the safety distance is a distance to prevent the assist pattern from being transferred to a photoresist layer during a lithography process. After the OPC is performed, the adjacent portion is shifted to increase the first distance to a second distance, wherein the second distance is greater than or equal to the safety distance.

Abstract: A capacitor device, such as a metal insulator metal (MIM) capacitor includes a seed layer including tantalum, a first electrode on the seed layer, where the first electrode includes at least one of ruthenium or iridium and an insulator layer on the seed layer, where the insulator layer includes oxygen and one or more of Sr, Ba or Ti. In an exemplary embodiment, the insulator layer is a crystallized layer having a substantially smooth surface. A crystallized insulator layer having a substantially smooth surface facilitates low electrical leakage in the MIM capacitor. The capacitor device further includes a second electrode layer on the insulator layer, where the second electrode layer includes a second metal or a second metal alloy.

Abstract: The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, a PN junction assembly, and a transistor circuit. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer is formed above the second surface. The second metal layer is formed on the second surface. The PN junction assembly is disposed on the first surface and electrically connected with the first metal layer and the second metal layer. The PN junction assembly includes a variable capacitor. The transistor circuit is electrically connecting with the second metal layer.

Abstract: An electronic device is provided. The electronic device includes a substrate, a conductive layer, an insulating layer, and a modulating material. The conductive layer is disposed on the substrate and has a first opening penetrating through the conductive layer. The insulating layer is disposed on the conductive layer and includes a second opening penetrating through the insulating layer. The first opening of the conductive layer and the second opening of the insulating layer are at least partially overlapped. The modulating material is disposed on the insulating layer.

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

Abstract: The disclosure provides an electronic apparatus. The electronic apparatus includes an insulator, a driving unit, an electronic unit, and a circuit unit. The driving unit is overlapped with the insulator. The electronic unit is overlapped with the insulator. The circuit unit is electrically connected to the driving unit. The driving unit receives a signal from the circuit unit and drives the electronic unit.

Abstract: This document describes methods and systems for an antenna system integrated with side-keys of an electronic device. The antenna system enables antenna integration in a metal frame using a metal support structure and fastener(s) to route antenna signals around side-key modules embedded in the frame without encountering or causing interference with the side-key modules. By using these techniques to integrate antennas on areas around the side-key modules, more antennas can be implemented on the electronic device, leading to improved capabilities supporting additional wireless standards and a better user experience in terms of improved communication quality.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.