Abstract: A power supply circuit, its generating and control methods are presented, relating to smart wearable devices. The power supply circuit comprises a Bandgap voltage reference, a real-time detection and control circuit, and a substitute voltage source. The real-time detection and control circuit is connected to the Bandgap voltage reference and the substitute voltage source, and adjusts an output voltage of the substitute voltage source to match an output voltage of the Bandgap voltage reference. After these output voltages are equal, the output voltage of the power supply circuit is provided by the substitute voltage source, and the Bandgap voltage reference can be disconnected from the circuit. This circuit can lower the power consumption of the Bandgap voltage reference without affecting the stability of the voltage output.

Abstract: Circuits and methods for measuring a working current of a circuit module. An exemplary circuit for measuring a working current of a circuit module includes a capacitor. The capacitor supplies a voltage to the circuit module using a voltage on the two terminals of the capacitor. The circuit also includes a voltage measuring module. The voltage measuring module measures a voltage change amount on the two terminals of the capacitor in an unit time. The working current of the circuit module is determined by the circuit according to the voltage change amount on the two terminals of the capacitor in the unit time and a capacitance of the capacitor.

Abstract: Method and device for detecting the process corner of a transistor are provided. The process corner detection method includes providing a ring oscillator. The ring oscillator includes an odd number of oscillation units connected in series and an output port of one of the oscillation units serves as the output port of the ring oscillator to output an oscillation signal. Each oscillation unit is constructed based on a PMOS transistor and an NMOS transistor. The process corner detection method further includes measuring the period of the oscillation signal and the maintaining time of the oscillation signal at a high level and a low level in each cycle; and determining the process corner of the PMOS transistor and the NMOS transistor in the oscillation unit based on the period of the oscillation signal and the maintaining time of the oscillation signal at a high level and a low level in each cycle.

Abstract: Level-shifter circuits and methods of using the same are provided. A level-shifter circuit includes a latch unit and a level-shifting unit. The latch unit is configured to generate a latch signal for storing a logic state of a first digital signal in a first power supply domain. The level-shifting unit is configured to shift a voltage of the latch signal to output a second digital signal in a second power supply domain. The latch unit and the level-shifting unit are powered by a power supply voltage in the second power supply domain.

Abstract: A method operates a bandgap voltage reference circuit that includes a bias circuit for receiving a feedback signal and outputting a bias signal, an amplifier for receiving the bias signal and outputting a first reference signal as the feedback signal, an output circuit for receiving the first reference signal and outputting a second reference signal, and an output switch for outputting the second reference signal as an output signal. The method includes, after powering up the bandgap voltage reference circuit, determining whether the output signal is stable, when the output signal is stable, turning off the output switch; turning off the bias circuit; and turning off the output circuit. The sequential turning off the output switch, the output circuit, and the bias circuit puts the bandgap voltage reference circuit into a sleep mode to save power.

Abstract: The present disclosure provides Efuse bit cells and read/write methods thereof, and Efuse arrays. An exemplary Efuse bit cell includes a data latch configured to latch data of the Efuse bit cell, having two branches with a fuse disposed in a first branch and a resistor disposed in a second branch; a selection controller configured to control connections between one terminal of the first branch and a power source and between one terminal of the second branch and the power source, another terminal of the first branch and another terminal of the second branch being connected to ground; a first diode and a second diode, one of the first diode and the second diode being configured to input a write data signal; and a pass unit configured to transmit data stored in the Efuse bit cell and output a bit line signal.

Abstract: The present disclosure provides circuits and methods for generating clock-signals. An exemplary clock-signal generation circuit includes a delay buffer unit; an inverter unit coupled to the delay buffer unit; a first delay unit having a first NAND Boolean calculation sub unit, a first sub delay unit and a first level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a first delayed clock-signal; and a second delay unit having a second NAND Boolean calculation sub unit, a second sub delay unit and a second level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a second delayed clock signal.

Abstract: An electrical fuse (eFuse) array includes eFuse cells arranged in multiple rows and columns. Each eFuse cell has an eFuse, a first diode, and a second diode coupled to an internal node, each eFuse cell further having first, second, and third terminals coupled, respectively, to the first diode, the second diode, and the eFuse. The eFuse array further includes a shared NMOSFET for each of the multiple rows, with a drain coupled to the third terminal of each of the plurality of eFuse cells in that row and a gate coupled to a word line. Each column includes a write bit line coupled to the second terminal of each of the eFuse cells in that column, and a read bit line coupled to the first terminal of the eFuse cell.

Abstract: A array of electrically programmable fuse (eFuse) units includes at least one connecting switch connecting two adjacent eFuse units. Each eFuse unit includes an eFuse, a write switch for passing through a first portion of a write current, a read/write switch for passing through a second portion of the write current or a read current, and a common node. The eFuse, the write switch, the read/write switch, and the at least one connecting switch are connected to each other at the common node. By turning on and off the at least one connecting switch, the current is split among the eFuse units, so that the size of the write switch can be reduced, thus reducing the total area of the array.

Abstract: A voltage-adjusting device is provided for adjusting voltages of one or more power domains in a chip. The device includes a distributing system, and a voltage-adjusting system. The distributing system obtains task information for the one or more power domains, obtains a forecasted voltage and a detected voltage for a power domain, and obtains a control system for the power domain for controlling a voltage applied on the power domain based on the forecasted voltage and the detected voltage. The forecasted voltage is a voltage required for the power domain to execute a task. Further, the voltage-adjusting system is connected to the distributing system and the one or more power domains, adjusts the voltage applied on the power domain based on the control signal such that the detected voltage reaches the forecasted voltage when the power domain executes a task.

Abstract: A array of electrically programmable fuse (eFuse) units includes at least one connecting switch connecting two adjacent eFuse units. Each eFuse unit includes an eFuse, a write switch for passing through a first portion of a write current, a read/write switch for passing through a second portion of the write current or a read current, and a common node. The eFuse, the write switch, the read/write switch, and the at least one connecting switch are connected to each other at the common node. By turning on and off the at least one connecting switch, the current is split among the eFuse units, so that the size of the write switch can be reduced, thus reducing the total area of the array.

Abstract: The present disclosure provides an electronic display device including a backlight module, a light sensor, a storage device, an embedded controller, and a processing unit. The light sensor detects ambient light surrounding the electronic display device. The embedded controller controls intensity of the backlight module according to the ambient light and a brightness table of the storage device. The processing unit performs a basic input/output system to draw a brightness curve diagram according to the brightness table for users to adjust the curve of the brightness curve diagram during a boot process of the electronic display device and update the brightness table in the storage device according to the adjusted brightness curve diagram in response to a storing signal.

Abstract: An electrical fuse (eFuse) array includes eFuse cells arranged in multiple rows and columns. Each eFuse cell has an eFuse, a first diode, and a second diode coupled to an internal node, each eFuse cell further having first, second, and third terminals coupled, respectively, to the first diode, the second diode, and the eFuse. The eFuse array further includes a shared NMOSFET for each of the multiple rows, with a drain coupled to the third terminal of each of the plurality of eFuse cells in that row and a gate coupled to a word line. Each column includes a write bit line coupled to the second terminal of each of the eFuse cells in that column, and a read bit line coupled to the first terminal of the eFuse cell.

Abstract: The present disclosure provides Efuse bit cells and read/write methods thereof, and Efuse arrays. An exemplary Efuse bit cell includes a data latch configured to latch data of the Efuse bit cell, having two branches with a fuse disposed in a first branch and a resistor disposed in a second branch; a selection controller configured to control connections between one terminal of the first branch and a power source and between one terminal of the second branch and the power source, another terminal of the first branch and another terminal of the second branch being connected to ground; a first diode and a second diode, one of the first diode and the second diode being configured to input a write data signal; and a pass unit configured to transmit data stored in the Efuse bit cell and output a bit line signal.

Abstract: A method for operating a memory is provided. The memory has an array of memory cells arranged in a plurality of rows and columns. Each row includes a label storage unit. The method includes receiving a first to-be-programmed data set to be stored into a target row and determining whether a condition is satisfied. When the condition is satisfied, performing a first operation on the first to-be-programmed data set to obtain a second to-be-programmed data set, programming the second to-be-programmed data set into the target row of memory cells, and setting the value of the label storage, unit to be a first labeling value. When the condition is not satisfied, performing a second operation on the first to-be-programmed data set to program the first to-be-programmed data set into the target row of memory cells, and setting the value of the label storage unit to be a second labeling value.

Abstract: An item with fibers may be picked up and placed using a tool head with hooks that engage the fibers. The tool head may comprise at least one hook portion and at least one contact surface adjacent to the hook portion. The hooks that engage the fibers may extend from the hook portion. The tool head may be actuatable between at least a first configuration that permits the hooks to engage the fibers and a second configuration that does not permit the hooks to engage the fibers. An item may be picked up at a starting location with a tool head in the first configuration and placed at a placement location by moving the tool head and then actuating the tool head to the second configuration.

Abstract: The present disclosure provides circuits and methods for generating clock-signals. An exemplary clock-signal generation circuit includes a delay buffer unit; an inverter unit coupled to the delay buffer unit; a first delay unit having a first NAND Boolean calculation sub unit, a first sub delay unit and a first level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a first delayed clock-signal; and a second delay unit having a second NAND Boolean calculation sub unit, a second sub delay unit and a second level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a second delayed clock signal.

Abstract: A method may be used for designing an electrical circuit. The method may be implemented using a device that includes hardware. The method may include the following steps: generating a schematic model that represents the electrical circuit; placing representations of a set of elements of the electrical circuit for forming a pre-route layout model; and using the pre-route layout model and a set of layout-dependent effect parameter values to perform a pre-route simulation. The set of layout-dependent effect parameter values may pertain to the set of elements of the electrical circuit.

Abstract: A method for operating a memory is disclosed. The memory has an array of memory cells arranged in a plurality of rows and columns. Each row includes a label storage unit. The method includes receiving a first to-be-programmed data set to be stored into a target row and determining whether a condition is satisfied. When the condition is satisfied, performing a first operation on the first to-be-programmed data set to obtain a second to-be-programmed data set, programming the second to-be-programmed data set into the target row of memory cells, and setting the value of the label storage, unit to be a first labeling value. When the condition is not satisfied, performing a second operation on the first to-be-programmed data set to program the first to-be-programmed data set into the target row of memory cells, and setting the value of the label storage unit to be a second labeling value.

Abstract: An item with fibers may be picked up and placed using a tool head with hooks that engage the fibers. The tool head may comprise at least one hook portion and at least one contact surface adjacent to the hook portion. The hooks that engage the fibers may extend from the hook portion. The tool head may be actuatable between at least a first configuration that permits the hooks to engage the fibers and a second configuration that does not permit the hooks to engage the fibers. An item may be picked up at a starting location with a tool head in the first configuration and placed at a placement location by moving the tool head and then actuating the tool head to the second configuration.