Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

Abstract: In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.

Abstract: In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.

Abstract: A two-step etch technique is used in a continuous polysilicon on oxide definition edge (CPODE) recess process to form a recess in which the CPODE structure is to be formed. The two-step process includes performing a first etch operation using an isotropic etch technique, in which a recess in a dummy gate structure is formed to a first depth. A second etch operation is performed using anisotropic etch technique to form the recess to a second depth. The use of the anisotropic etch technique results in a highly directional (e.g., vertical) etch of the dummy gate structure in the second etch operation. The highly directional etch provided by the anisotropic etch technique at or near the bottom of the dummy gate structure reduces, minimizes, and/or prevents etching into adjacent portions of an interlayer dielectric (ILD) layer and/or into source/drain region(s) under the portions of the ILD layer.

Abstract: A method includes determining a target etching depth for etching a plurality of dielectric regions in a wafer. The wafer includes a plurality of protruding semiconductor fins and the plurality of dielectric regions between the plurality of protruding semiconductor fins. The method further includes etching the plurality of dielectric regions, projecting a light beam on the wafer, and generating a spectrum from a reflected light reflected from the wafer, determining an end point for etching based on the spectrum. The end point is an expected time point. The plurality of dielectric regions are etched to the target etching depth. The etching of the plurality of dielectric regions is stopped at the end point.

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

Abstract: In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.

Abstract: In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

Abstract: A diaphragm structure is used for an audio signal output device. The diaphragm structure includes a film substrate, a polymer fiber structure and a thin film metallic glass. The film substrate includes a first surface and a second surface opposite to the first surface. The polymer fiber structure is combined with the first surface of the film substrate. The thin film metallic glass is formed on at least a part of the second surface of the film substrate.

Abstract: In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.

Abstract: A diaphragm structure is used for an audio signal output device. The diaphragm structure includes a film substrate, a polymer fiber structure and a thin film metallic glass. The film substrate includes a first surface and a second surface opposite to the first surface. The polymer fiber structure is combined with the first surface of the film substrate. The thin film metallic glass is formed on at least a part of the second surface of the film substrate.

Abstract: The driving system for driving a display panel includes a timing controller and a source driving circuit. The source driving circuit includes a plurality of output channels and a plurality of shift registers respectively corresponding to the output channels. The plurality of shift registers are classified into a plurality of shift register series, among which a first shift register series includes a first shift register being as one end and a second shift register being as the other end, and a second shift register series includes a third shift register being as one end and a fourth shift register being as the other end. The timing controller is connected to the first shift register, the second shift register, the third shift register, and the fourth shift register, and transmits a first start pulse to the first shift register and a second start pulse to the third shift register.

Abstract: A thin film metallic glass coated needle includes a needle body, a needle head and a thin film metallic glass in amorphous structure and formed on a surface of the needle head and a surface of the needle body to reduce a surface energy and coefficient of friction. The thin film metallic glass is a titanium based comprising 35-45 at % titanium, 5-15 at % zirconium, 32-42 at % copper, 1-11 at % niobium and 2-12 at % cobalt.

Abstract: The present disclosure provides a thermoelectric structure including a thermoelectric substrate and a barrier layer covering the thermoelectric substrate. A material of the barrier layer is metallic glass. The thermoelectric structure of the present disclosure may apply to a medium-temperature (about 400K to about 800K) thermoelectric module to effectively block the diffusion of the thermoelectric substrate.

Abstract: The driving system for driving a display panel includes a timing controller and a source driving circuit. The source driving circuit includes a plurality of output channels and a plurality of shift registers respectively corresponding to the output channels. The plurality of shift registers are classified into a plurality of shift register series, among which a first shift register series includes a first shift register being as one end and a second shift register being as the other end, and a second shift register series includes a third shift register being as one end and a fourth shift register being as the other end. The timing controller is connected to the first shift register, the second shift register, the third shift register, and the fourth shift register, and transmits a first start pulse to the first shift register and a second start pulse to the third shift register.

Abstract: A thin film metallic glass coated needle includes a needle body, a needle head and a thin film metallic glass in amorphous structure and formed on a surface of the needle head and a surface of the needle body to reduce a surface energy and coefficient of friction. The thin film metallic glass is a titanium based comprising 35-45 at % titanium, 5-15 at % zirconium, 32-42 at % copper, 1-11 at % niobium and 2-12 at % cobalt.

Abstract: A method for a source driving circuit utilized in a display device includes receiving an input signal by a first reception module at a first period, receiving the input signal by the first reception module and a second reception module at a second period after the first period, receiving the input signal by the second reception module and a third reception module at a third period after the second period, and outputting the input signal received by the first reception module, the second reception module and the third reception module to a display panel after the third reception module finishes reception of the input signals, wherein the second reception module is disposed between the first reception module and the third reception module.