Patents by Inventor Chia-Chiang Lin

Chia-Chiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11129036
    Abstract: Methods and apparatuses estimating pathloss of PUSCH in a wireless communication system are disclosed herein. In one method, the UE receives a first configuration of a first serving cell and a second serving cell, wherein the second serving cell is a pathloss reference for the first serving cell. The UE receives a second configuration of multiple downlink bandwidth parts of the second serving cell, wherein a downlink bandwidth part among the multiple downlink bandwidth parts is an active downlink bandwidth part. The UE estimates (or derives) a pathloss for an uplink transmission in an uplink bandwidth part of the first serving cell based on a reference signal in the downlink bandwidth part.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: September 21, 2021
    Assignee: ASUSTek Computer Inc.
    Inventors: Chia-Chi Lu, Ko-Chiang Lin
  • Patent number: 11121308
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin
  • Publication number: 20210273103
    Abstract: A method includes providing a structure having a substrate and a fin. The fin has first and second layers of first and second different semiconductor materials. The first layers and the second layers are alternately stacked over the substrate. The structure further has a sacrificial gate stack engaging a channel region of the fin and gate spacers on sidewalls of the sacrificial gate stack. The method further includes etching a source/drain (S/D) region of the fin, resulting in an S/D trench; partially recessing the second layers exposed in the S/D trench, resulting in a gap between two adjacent layers of the first layers; and depositing a dielectric layer over surfaces of the gate spacers, the first layers, and the second layers. The dielectric layer partially fills the gap, leaving a void sandwiched between the dielectric layer on the two adjacent layers of the first layers.
    Type: Application
    Filed: July 31, 2020
    Publication date: September 2, 2021
    Inventors: Shih-Chiang Chen, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
  • Publication number: 20210263243
    Abstract: In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lun Chang, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hsuan-Ting Kuo, Chia-Shen Cheng, Chih-Chiang Tsao
  • Publication number: 20210233954
    Abstract: A detection panel and a manufacturing method thereof are disclosed. The detection panel (200) includes a first substrate (21) and a second substrate (22), and the first substrate (21) includes a light detection layer (213); the second substrate (22) includes a drive circuit (205); the first substrate (21) and the second substrate (22) are opposite to each other for cell assembly, and the drive circuit (205) is coupled to the light detection layer (213) to read a photosensitive signal generated by the light detection layer (213). By forming the light detection layer (213) and the drive circuit (205) on different substrates, the detection panel (200) contributes to increase the flatness of the light detection layer (213) and reduce the defects of the light detection layer (213), thereby reducing the leakage current in a dark state and improving the performance of the detection panel (200).
    Type: Application
    Filed: January 16, 2020
    Publication date: July 29, 2021
    Inventors: Gang HUA, Chuncheng CHE, Cheng LI, Jian WANG, Yanna XUE, Yong ZHANG, Chia Chiang LIN
  • Publication number: 20210202779
    Abstract: A flat panel detector and a manufacturing method thereof. The flat panel detector includes a first substrate and a second substrate. The first substrate includes a driving circuit, the second substrate includes a photosensitive element, the first substrate and the second substrate are arranged opposite to each other so as to be assembled, and the driving circuit is electrically connected with the photosensitive element to drive the photosensitive element. The flat panel detector not only can improve the filling rate of a photodiode in a pixel unit and increase the photosensitive area of the pixel unit in the flat panel detector, but also can effectively prevent static electricity and scratches generated during use and improve the photoelectric characteristics and yield of the flat panel detector.
    Type: Application
    Filed: December 9, 2019
    Publication date: July 1, 2021
    Inventors: Xuecheng HOU, Chia Chiang LIN, Chuncheng CHE
  • Patent number: 10732482
    Abstract: A liquid crystal lens and a manufacturing method thereof, and a display device are provided. The liquid crystal lens includes: an upper substrate, a lower substrate, a liquid crystal layer arranged between the upper substrate and the lower substrate; at least one first electrode arranged at a side, close to the liquid crystal layer, of the upper substrate; and at least one second electrode and at least one third electrode which are arranged at a side, close to the liquid crystal layer, of the lower substrate. The liquid crystal layer includes a first region over the second electrode and a second region over the third electrode. Liquid crystals in both the first region and the second region have a tilted angle, and alignment directions of the liquid crystals in the first region and the second region are opposite to each other.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: August 4, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Chia Chiang Lin
  • Patent number: 10622388
    Abstract: Disclosed are an array substrate, a manufacturing method thereof, a sensor and a detection device. The array substrate includes: a base substrate; a thin-film transistor (TFT) being disposed on the base substrate and including a source electrode and an active layer; a passivation layer disposed on the TFT; a first metal layer disposed on the passivation layer; an insulating layer disposed on the first metal layer; a through hole structure running through the insulating layer, the first metal layer and the passivation layer; and a detection unit being disposed on the insulating layer and including a second metal layer, wherein the second metal layer makes direct contact with the source electrode via the through hole structure.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: April 14, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., KA IMAGING INC.
    Inventor: Chia Chiang Lin
  • Patent number: 10573305
    Abstract: Disclosed is a voice control system and method thereof. The voice control system is used in an electronic device and works in a sleep mode and a working mode. The voice control system comprises an audio detection module, an audio codec and a control module. Under the sleep mode, the audio detection module continually detects whether there is a wake-up speech in a received first audio data. If yes, the audio detection module generates a first indication signal and temporarily stores the following first audio data. When the control module is woken up by the first indication signal, the voice control system enters the working mode. Under the working mode, the control module drives the audio codec to read and process the temporarily stored first audio data to recognize control speech in the first audio data and to accordingly control the electronic device.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: February 25, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chia-Chiang Lin, Yi-Huan Wang
  • Patent number: 10317721
    Abstract: Embodiments of the present invention disclose a dual-view field display panel comprising: a first substrate and a second substrate disposed opposite to the first substrate; and a dual-view grating disposed on a side of the first substrate away from the second substrate, which has a plurality of elongated transparent areas spaced from each other; wherein each of the plurality of elongated transparent areas corresponds to a plurality of rows of pixels and is substantially parallel therewith, and the number of rows of the plurality of rows of pixels corresponding to each of the plurality of elongated transparent areas is selected based on the thickness of the first substrate, so that light from the plurality of rows of pixels is able to be viewed in the left-view field or in the right-view field through a corresponding transparent area.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: June 11, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chia-Chiang Lin, Wei Wei
  • Patent number: 10311809
    Abstract: A dual view-field display and a fabricating method and a driving method thereof are provided. The dual view-field display includes a color filter substrate and an array substrate which are oppositely disposed. A slit grating is disposed on a side of the color filter substrate or the array substrate, and the color filter substrate includes a plurality of pixel units and a first black matrix surrounding each pixel unit. The slit grating includes light-shielding regions and light-transmitting regions, which are arranged at intervals in a matrix. The dual view-field display further comprises a light blocking portion configured for preventing light rays from leaking out of an upper-edge region and/or a lower-edge region of the light-transmitting region, which solves a problem that a viewing angle of a user of the dual view-field display is limited.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: June 4, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chia Chiang Lin, Yanbing Wu
  • Publication number: 20190165007
    Abstract: Disclosed are an array substrate, a manufacturing method thereof, a sensor and a detection device. The array substrate includes: a base substrate; a thin-film transistor (TFT) being disposed on the base substrate and including a source electrode and an active layer; a passivation layer disposed on the TFT; a first metal layer disposed on the passivation layer; an insulating layer disposed on the first metal layer; a through hole structure running through the insulating layer, the first metal layer and the passivation layer; and a detection unit being disposed on the insulating layer and including a second metal layer, wherein the second metal layer makes direct contact with the source electrode via the through hole structure.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 30, 2019
    Inventor: Chia Chiang LIN
  • Patent number: 10269837
    Abstract: A sensor, a manufacturing method thereof and an electronic device. The sensor includes: a base substrate; a thin-film transistor (TFT) disposed on the base substrate and including a source electrode; a first insulation layer disposed on the TFT and provided with a first through hole running through the first insulation layer; a conductive layer disposed in the first through hole and on part of the first insulation layer and electrically connected with the source electrode via the first through hole; a bias electrode disposed on the first insulation layer and separate from the conductive layer; a sensing active layer respectively connected with the conductive layer and the bias electrode; and an auxiliary conductive layer disposed on the conductive layer. The sensor and the manufacturing method thereof improve the conductivity and ensure normal transmission of signals by arranging the auxiliary conductive layer on the conductive layer without addition of processes.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 23, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., KA IMAGING INC.
    Inventor: Chia Chiang Lin
  • Patent number: 10224353
    Abstract: Disclosed are an array substrate, a manufacturing method thereof, a sensor and a detection device. The array substrate includes: a base substrate; a thin-film transistor (TFT) being disposed on the base substrate and including a source electrode and an active layer; a passivation layer disposed on the TFT; a first metal layer disposed on the passivation layer; an insulating layer disposed on the first metal layer; a through hole structure running through the insulating layer, the first metal layer and the passivation layer; and a detection unit being disposed on the insulating layer and including a second metal layer, wherein the second metal layer makes direct contact with the source electrode via the through hole structure.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: March 5, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., KA IMAGING INC.
    Inventor: Chia Chiang Lin
  • Patent number: 10210839
    Abstract: Embodiments of the disclosure relate to a pixel structure for naked-eye stereoscopic display, which comprises: a main display region; and at least one crosstalk region. The main display region and the crosstalk region are configured such that brightness of the main display region and brightness of the crosstalk region are controlled separately. Embodiments of the disclosure also relate to an array substrate for use with an inclined optical grating, and a method for controlling the pixel structure of the array substrate.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 19, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chia-Chiang Lin, Wei Wei
  • Patent number: 10126710
    Abstract: A spatial light modulator and a method for displaying a computer generated hologram are disclosed. The spatial light modulator includes a plurality of MEMS units arranged in an array, each of the MEMS units corresponds to a pixel of a computer generated hologram and includes a sensing device, a light shielding portion and a driving device. The sensing device is configured for receiving position information that is obtained through Roman encoding a pixel corresponding to an MEMS unit including the sensing device and the position information is transmitted to the driving device by the sensing device. The driving device is configured for controlling the light shielding portion to move to a position corresponding to the position information in response to the received position information of the light shielding portion when the present frame is displayed.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: November 13, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Naifu Wu, Bei Niu, Tao Wang, Wei Wei, Kun Wu, Chia Chiang Lin, Chunmiao Zhou
  • Patent number: 10102167
    Abstract: This invention discloses a data processing circuit and a data processing method. The data processing method controls data transmission between a USB control unit and a USB interface, and includes the steps of: detecting a voltage of a configuration channel pin of the USB interface to generate a detection signal; determining whether the USB control unit and the USB interface are connected according to the detection signal; and performing an audio signal processing procedure when the USB control unit and the USB interface are not connected.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: October 16, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Chia-Chiang Lin
  • Patent number: 10073274
    Abstract: A grating, a manufacturing method thereof and a display device are disclosed. The grating comprises: a substrate including a plurality of first view field regions (A1) and a plurality of second view field regions (A2) which are alternately distributed; a plurality of ridge structures formed on the substrate in each first view field region (A1) and each second view field region (A2); and a patterned light shield layer being formed on the ridge structures and including a plurality of light-blocking regions and a plurality of light-transmitting regions, wherein in each first view field region (A1), each light-transmitting region is formed on a sloping surface of a first side of each ridge structure; in each second view field region (A2), each light-transmitting region is formed on a sloping surface of a second side of each ridge structure; and the first side and the second side are two opposite sides.
    Type: Grant
    Filed: November 28, 2014
    Date of Patent: September 11, 2018
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Chia Chiang Lin
  • Publication number: 20180122841
    Abstract: A sensor, a manufacturing method thereof and an electronic device. The sensor includes: a base substrate; a thin-film transistor (TFT) disposed on the base substrate and including a source electrode; a first insulation layer disposed on the TFT and provided with a first through hole running through the first insulation layer; a conductive layer disposed in the first through hole and on part of the first insulation layer and electrically connected with the source electrode via the first through hole; a bias electrode disposed on the first insulation layer and separate from the conductive layer; a sensing active layer respectively connected with the conductive layer and the bias electrode; and an auxiliary conductive layer disposed on the conductive layer. The sensor and the manufacturing method thereof improve the conductivity and ensure normal transmission of signals by arranging the auxiliary conductive layer on the conductive layer without addition of processes.
    Type: Application
    Filed: September 21, 2016
    Publication date: May 3, 2018
    Inventor: Chia Chiang LIN
  • Publication number: 20180114802
    Abstract: Disclosed are an array substrate, a manufacturing method thereof, a sensor and a detection device. The array substrate includes: a base substrate; a thin-film transistor (TFT) being disposed on the base substrate and including a source electrode and an active layer; a passivation layer disposed on the TFT; a first metal layer disposed on the passivation layer; an insulating layer disposed on the first metal layer; a through hole structure running through the insulating layer, the first metal layer and the passivation layer; and a detection unit being disposed on the insulating layer and including a second metal layer, wherein the second metal layer makes direct contact with the source electrode via the through hole structure.
    Type: Application
    Filed: January 10, 2017
    Publication date: April 26, 2018
    Inventor: Chia Chiang LIN