Patents by Inventor Chia-Chiang Tsai

Chia-Chiang Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11996400
    Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. Top packages are mounted on a top side of a reconstructed wafer over a flexible tape, where conductive bumps at a bottom side of the reconstructed wafer is attached to the flexible tape, and during the mounting, a shape geometry of the respective conductive bump changes and at least a lower portion of the respective conductive bump is embraced by the flexible tape. The flexible tape is released from the conductive bumps after the mounting.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-Shuan Chung
  • Patent number: 11990474
    Abstract: A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu Fang Fu, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Fu-Huan Tsai
  • Publication number: 20240145403
    Abstract: An electronic package is provided, in which electronic elements and at least one packaging module including a semiconductor chip and a shielding structure covering the semiconductor chip are disposed on a carrier structure, an encapsulation layer encapsulates the electronic elements and the packaging module, and a shielding layer is formed on the encapsulation layer and in contact with the shielding structure. Therefore, the packaging module includes the semiconductor chip and the shielding structure and has a chip function and a shielding wall function simultaneously.
    Type: Application
    Filed: February 6, 2023
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chih-Chiang HE, Ko-Wei CHANG, Chia-Yang CHEN
  • Patent number: 11935957
    Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Publication number: 20240088224
    Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: HSING-I TSAI, FU-HUAN TSAI, CHIA-CHUNG CHEN, HSIAO-CHUN LEE, CHI-FENG HUANG, CHO-YING LU, VICTOR CHIANG LIANG
  • Patent number: 8773727
    Abstract: A image generating apparatus and method for scanning documents using multiple image sensors are disclosed. The image generation apparatus comprises a glass plate configured to hold a document placed upside down on the glass plate; a calibration pattern placed on the glass plate; a plurality of image sensors arranged under the glass plate, wherein each of the plurality of image sensors is configured to capture and generate a raw image, the raw image covers a portion of the document and a portion of the calibration pattern through the glass plate; and a processing unit capable of combining all raw images generated by the plurality of image sensors based on the portion of the calibration pattern in the raw image captured by each of the plurality of image sensors, and the processing unit is further configured to generate a complete image of the document.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 8, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Chia-Chiang Tsai
  • Publication number: 20120268800
    Abstract: A image generating apparatus and method for scanning documents using multiple image sensors are disclosed. The image generation apparatus comprises a glass plate configured to hold a document placed upside down on the glass plate; a calibration pattern placed on the glass plate; a plurality of image sensors arranged under the glass plate, wherein each of the plurality of image sensors is configured to capture and generate a raw image, the raw image covers a portion of the document and a portion of the calibration pattern through the glass plate; and a processing unit capable of combining all raw images generated by the plurality of image sensors based on the portion of the calibration pattern in the raw image captured by each of the plurality of image sensors, and the processing unit is further configured to generate a complete image of the document.
    Type: Application
    Filed: December 20, 2011
    Publication date: October 25, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: CHIA-CHIANG TSAI
  • Publication number: 20090274486
    Abstract: A drive roller is adapted for use with an image forming device that includes a conveyer belt trained on the drive roller. The drive roller includes an elongated roller body and symmetrical first and second threads. The roller body has a first segment that has an annular first surrounding surface, and a second segment that is opposite to the first segment, that has a length equal to that of the first segment, and that has an annular second surrounding surface. The first and second threads are formed respectively at the first and second surrounding surfaces, are threaded in opposite directions, and are adapted for contacting the conveyer belt.
    Type: Application
    Filed: October 16, 2008
    Publication date: November 5, 2009
    Inventor: Chia-Chiang Tsai