Patents by Inventor Chia-Chiang Wang

Chia-Chiang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955507
    Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: April 9, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
  • Publication number: 20080079102
    Abstract: A method for fabricating an image sensor structure is provided. The method of fabricating an image sensor structure includes providing a substrate. An image sensor interconnect structure is formed on the substrate. A patterned stop layer is formed on the image sensor interconnect structure. An electrode layer, a first doped amorphous silicon layer and a first undoped amorphous silicon layer are conformably formed on the patterned stop layer and the image sensor interconnect structure not covered by the patterned stop layer in sequence. The first undoped amorphous silicon layer, the first doped amorphous silicon layer and the electrode layer are partially removed until the patterned stop layer is exposed by a planarization process, and each of a remaining electrode layer, a remaining first doped amorphous silicon layer and a remaining first undoped amorphous silicon layer are separated by the patterned stop layer.
    Type: Application
    Filed: February 15, 2007
    Publication date: April 3, 2008
    Inventors: Yu-Hsien Chen, Min-San Huang, Chia-Chiang Wang
  • Publication number: 20080057614
    Abstract: A color image sensor device and fabrication method thereof. A passivation layer and a first planarization layer are sequentially formed on a substrate. A plurality of color filter elements are disposed over the first planarization layer corresponding to the sensor pixel array. A second planarization layer and a third planarization layer are sequentially formed over the first planarization layer. The third planarization layer has an opening formed corresponding to a contact pad. A third opening in the first planarization layer and the passivation layer corresponds to the contact pad.
    Type: Application
    Filed: November 1, 2007
    Publication date: March 6, 2008
    Inventors: Tsai Shian-Ching, Chung Sian-Min, Chia-Chiang Wang, Yu-Wan Chen, Chen Lan, Fu Lee
  • Publication number: 20070158707
    Abstract: An image sensor including a substrate, a plurality of conductive sections, a first type doped layer, an intrinsic layer, and a transparent electrode layer is provided. Wherein, the conductive sections are disposed on the substrate, and the dielectric layer is disposed between two adjacent conductive sections. In addition, the first type doped layer overlays the conductive sections and the dielectric layer, and the intrinsic layer is disposed on the first type doped layer. Moreover, the transparent electrode layer is disposed on the intrinsic layer.
    Type: Application
    Filed: March 29, 2006
    Publication date: July 12, 2007
    Inventors: Min-San Huang, Sian-Min Chung, Chia-Chiang Wang, Yu-Chun Lin, Wen-Tsung Chiu, Hung-Nien Chen
  • Publication number: 20060208298
    Abstract: A DRAM cell including a trench capacitor structure, a transistor and a stacked capacitor structure is provided. A first electrode of the trench capacitor structure is disposed in the substrate at the bottom of a trench. A second electrode of the trench capacitor structure is disposed in the trench. The transistor includes a gate, first and second source/drain regions. The gate is disposed on the substrate beside the trench capacitor structure. The first and the second source/drain regions are disposed in the substrate on respective sides of the gate. A third electrode of the stacked capacitor structure is disposed on the substrate between the gate of the transistor and the trench capacitor structure. A fourth electrode of the stacked capacitor structure is disposed on the third electrode above the substrate. The first electrode connects electrically with the fourth electrode, and the second electrode connects electrically with the third electrode.
    Type: Application
    Filed: October 11, 2005
    Publication date: September 21, 2006
    Inventors: Ko-Hsing Chang, Chia-Chiang Wang