Abstract: Aspects of the present disclosure provide an automated labeling system. For example, the automated labeling system can include an automated labeling module (ALM) configured to receive wireless signals and ground truth of learning object and label the wireless signals with the ground truth when receiving the ground truth to generate labeled training data. The automated labeling system can also include a training database coupled to the ALM. The training database can be configured to store the labeled training data.

Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.

Abstract: A method of fabricating a polysilicon layer is provided. A substrate having a front surface and a back surface is provided. A buffer layer, an amorphous layer and a cap layer are sequentially formed on the front surface of the substrate. The cap layer is patterned to form a patterned cap layer exposing a portion of the amorphous layer, wherein the exposed portion of the amorphous layer is a crystallization initial region. A metallic catalytic layer is formed on the patterned cap layer, wherein the metallic catalytic layer contacts with the crystallization initial region of the amorphous layer. A laser annealing process is performed through the back surface of the substrate so that the amorphous layer is crystallized and transformed into a polysilicon layer from the crystallization initial region.

Abstract: A method for fabricating a thin film transistor is provided. First, a gate is formed on a substrate. A gate-insulating layer is formed to cover the gate. A patterned semiconductor layer is formed on the gate-insulating layer. A first and a second conductive layer are formed on the patterned semiconductor layer in sequence. The second conductive layer is patterned such that each side of thereof above the gate has a taper profile and the first conductive layer is exposed. A first plasma process is performed to transform the surface and the taper profile of the second conductive layer into a first protection layer. The first conductive layer not covered by the first protection layer and the second conductive layer is removed to form a source/drain. The source/drain is with fine dimensions and the diffusion of metallic ions from the second conductive layer to the patterned semiconductor layer can be avoided.

Abstract: A method for fabricating a thin film transistor is provided. First, a gate is formed on a substrate. A gate-insulating layer is formed to cover the gate. A patterned semiconductor layer is formed on the gate-insulating layer. A first and a second conductive layer are formed on the patterned semiconductor layer in sequence. The second conductive layer is patterned such that each side of thereof above the gate has a taper profile and the first conductive layer is exposed. A first plasma process is performed to transform the surface and the taper profile of the second conductive layer into a first protection layer. The first conductive layer not covered by the first protection layer and the second conductive layer is removed to form a source/drain. The source/drain is with fine dimensions and the diffusion of metallic ions from the second conductive layer to the patterned semiconductor layer can be avoided.

Abstract: A method for manufacturing a thin film transistor is provided. First, a poly-silicon island is formed on a substrate. Then, a patterned gate dielectric layer and a gate are formed on the poly-silicon island. Next, a source/drain is formed in the poly-silicon island beside the gate, wherein the region between the source/drain is a channel. Furthermore, a metal layer is formed on the substrate to cover the gate, the patterned gate dielectric layer and the poly-silicon island. Moreover, the metal layer above the source/drain will react with the poly-silicon island to form a silicide layer. Then, the non-reacted metal layer is removed. Afterwards, an inter-layer dielectric (ILD) is formed to cover the substrate. Then, the inter-layer dielectric above the source/drain is removed to form a source/drain contacting hole, wherein the silicide layer is used as an etching stopper.

Abstract: A method of forming a thin film transistor is provided. First, an amorphous silicon layer is formed on a substrate. Next, a first gate insulating layer is formed on the amorphous silicon layer. Then, an annealing process is performed so that the amorphous silicon layer is melted and re-crystallized to form a poly silicon layer. Next, the first insulating layer and the poly silicon layer are patterned to form an island. Then, a gate electrode is formed on the island. Finally, a source region and a drain region are formed inside the poly silicon layer of the island. After the annealing process is performed, the boundary between the poly silicon layer and the gate insulating layer becomes denser, so that the current leakage of the thin film transistor can be reduced.

Abstract: A thin film transistor having a substrate, a gate insulating layer, a double-gate structure, a first lightly doped region, and a second lightly doped region. The substrate has a source region and a drain region disposed on its opposite sides, a heavily doped region between source region and drain region, a first channel region between heavily doped region and source region and a second channel region between heavily doped region and drain region. The gate insulating layer covers the substrate. The double-gate structure has a first gate and a second gate disposed on gate insulating layer above the first and the second channel region, respectively. The first lightly doped region is disposed between second channel region and heavily doped region and the second lightly doped region between second channel region and drain region. The length of second lightly doped region is greater than that of first lightly doped region.