Abstract: A method of estimating a toggle count of a circuit, includes, in part, simulating the circuit to generate training data and an associated training toggle count of the internal nodes of the circuit in response to a test bench, training a neural network system to generate an estimate of the training toggle count in accordance with the training data and the associated training toggle count, simulating the circuit to generate simulation data in response to a first set of input values applied to the circuit, and invoking the trained neural network system to estimate a number of toggles of the internal nodes of the circuit from the simulation data. The training data may include, in part, values of input signals applied to the circuit and values of registers disposed in the circuit for a multitude of time stamps. The neural network system may include, in part, at least three layers.

Abstract: A method for performing glitch power analysis of a circuit, comprising receiving no-timing waveform simulation data for the circuit, the waveform simulation data including a first signal, and identifying a delayed stimulus injection point (DSIP) for the first signal. The method further comprises determining a total delay for the first signal and performing waveform replay simulation including injecting the first signal at the DSIP at a time based on the total delay for the first signal.

Abstract: In some aspects, a graph is used to assist users in cause analysis of faults. The graph represents signal flow through a design of an integrated circuit The graph includes graph elements, such as nodes and edges. The nodes may represent cells and nets in the circuit design, and the edges may represent signal flow between the cells and nets. A propagation model for the propagation of faults through the graph is constructed. The propagation model includes local propagation models for the propagation of faults through the graph elements. Propagation of a known fault backward through the graph is modeled using the propagation model. This results in a causality ranking of the graph elements as possible causes of the known fault. Information indicative of the causality ranking is displayed in a user interface that shows the design of the integrated circuit.

Abstract: Techniques for equivalence checking of analog models are disclosed. The models include transistor level representations. The representations are used for simulation and verification of the circuit and are required to give similar output results in response to a given input stimulus. A common input stimulus is created for a first representation and a second representation of a semiconductor circuit. Output waveforms are generated for the first representation and the second representation using the common input stimulus. The first output waveforms and the second output waveforms are checked for equivalence. Signals from the first output waveforms are mapped to the second output waveforms.

Abstract: Techniques for equivalence checking of analog models are disclosed. The models include transistor level representations. The representations are used for simulation and verification of the circuit and are required to give similar output results in response to a given input stimulus. A common input stimulus is created for a first representation and a second representation of a semiconductor circuit. Output waveforms are generated for the first representation and the second representation using the common input stimulus. The first output waveforms and the second output waveforms are checked for equivalence. Signals from the first output waveforms are mapped to the second output waveforms.

Abstract: What-if simulation methods and systems are provided. A design coding in HDL (Hardware Description Language) and a simulation result corresponding to the design are provided. A what-if design scope and a what-if time window are received. A portion of the design is extracted from the design according to the what-if design scope, and primary input signals are determined during the extraction of the sub-design. Then, what-if simulation data is extracted from the simulation result according to the primary input signals and the what-if time window. A what-if test bench is generated according to the what-if simulation data, wherein the what-if simulation data is read, and the signal values are fed to a simulator according to the what-if test bench.

Abstract: What-if simulation methods and systems are provided. A design coding in HDL (Hardware Description Language) and a simulation result corresponding to the design are provided. A what-if design scope and a what-if time window are received. A portion of the design is extracted from the design according to the what-if design scope, and primary input signals are determined during the extraction of the sub-design. Then, what-if simulation data is extracted from the simulation result according to the primary input signals and the what-if time window. A what-if test bench is generated according to the what-if simulation data, wherein the what-if simulation data is read, and the signal values are fed to a simulator according to the what-if test bench.