Abstract: A method for controlling device activation and an associated electronic device are provided. The method includes: utilizing a static entropy source of the electronic device to provide a static entropy; utilizing a first message authentication code (MAC) operator of the electronic device to execute a predetermined algorithm for generating a reference code according to the static entropy and an embedded key of the electronic device; receiving an activation code from outside of the electronic device; utilizing a comparing circuit to compare the activation code with the reference code for generating a comparison result; and determining whether to activate at least one functional circuit of the electronic device according to the comparison result.

Abstract: A method and a secure boot control circuit for controlling a secure boot of an electronic device. The method is applicable to the secure boot control circuit, and the electronic device includes the secure boot control circuit. The method includes: checking randomness of an output of an entropy source of the secure boot control circuit to generate a check result; utilizing the entropy source to provide a random number sequence; generating a reference code according to the random number sequence; comparing the reference code with an activation code stored in the secure boot control circuit to generate a comparison result; and determining whether to enable at least one function of the electronic device according to at least one of the check result and the comparison result.

Abstract: An electronic device and a method for performing permission management of a storage device are provided. The storage device includes multiple storage blocks. The electronic device includes a controller and multiple dedicated interfaces, wherein the multiple dedicated interfaces are coupled to multiple ports of the controller. The controller is configured to perform access control of the storage device. The multiple dedicated interfaces correspond to the multiple storage blocks, and each dedicated interface of the multiple dedicated interfaces is configured to provide a dedicated channel for accessing one of the multiple storage blocks corresponding to said each dedicated interface via the controller.

Abstract: An electronic device includes a first non-volatile memory and an application circuit. The first non-volatile memory stores first encrypted data encrypted with a global key. The application circuit includes a second non-volatile memory, a decryption unit, a local key unit, and an encryption unit. The second non-volatile memory stores the global key. The decryption unit is coupled to the first non-volatile memory and the second non-volatile memory. The decryption unit retrieves the global key from the second non-volatile memory and decrypts the first encrypted data with the global key to generate plain data. The local key unit generates or stores a local key. The encryption unit is coupled to the local key unit. The encryption unit encrypts the plain data with the local key to generate second encrypted data and overwrites the first encrypted data in the first non-volatile memory with the second encrypted data.

Abstract: A method for controlling device activation and an associated electronic device are provided. The method includes: utilizing a static entropy source of the electronic device to provide a static entropy; utilizing a first message authentication code (MAC) operator of the electronic device to execute a predetermined algorithm for generating a reference code according to the static entropy and an embedded key of the electronic device; receiving an activation code from outside of the electronic device; utilizing a comparing circuit to compare the activation code with the reference code for generating a comparison result; and determining whether to activate at least one functional circuit of the electronic device according to the comparison result.

Abstract: A method and a secure boot control circuit for controlling a secure boot of an electronic device. The method is applicable to the secure boot control circuit, and the electronic device includes the secure boot control circuit. The method includes: checking randomness of an output of an entropy source of the secure boot control circuit to generate a check result; utilizing the entropy source to provide a random number sequence; generating a reference code according to the random number sequence; comparing the reference code with an activation code stored in the secure boot control circuit to generate a comparison result; and determining whether to enable at least one function of the electronic device according to at least one of the check result and the comparison result.

Abstract: An electronic device includes a first non-volatile memory and an application circuit. The first non-volatile memory stores first encrypted data encrypted with a global key. The application circuit includes a second non-volatile memory, a decryption unit, a local key unit, and an encryption unit. The second non-volatile memory stores the global key. The decryption unit is coupled to the first non-volatile memory and the second non-volatile memory. The decryption unit retrieves the global key from the second non-volatile memory and decrypts the first encrypted data with the global key to generate plain data. The local key unit generates or stores a local key. The encryption unit is coupled to the local key unit. The encryption unit encrypts the plain data with the local key to generate second encrypted data and overwrites the first encrypted data in the first non-volatile memory with the second encrypted data.

Abstract: An electronic system includes a first circuit and a second circuit. The first circuit includes a first activation unit and a first functional unit. The first activation unit receives a first challenge string, generates a first response string according to the first challenge string and a first key, and outputs the first response string. The first functional unit performs first designated function. The second circuit includes a second activation unit and a second functional unit. The second activation unit sends the first challenge string to the first circuit during a first activation operation, and determines whether the first activation operation passes certification or not according to the first challenge string, the first response string and the first key. The second functional unit performs second designated function when the first activation operation is determined to have passed the certification.

Abstract: A computation system includes a first affine transform circuit, a second affine transform circuit, a computation circuit, a third affine transform circuit, and a fourth affine transform circuit. The first affine transform circuit transforms first input data of a first Galois field into first computing data of a common composite field. The second affine transform circuit transforms second input data of a second Galois field into second computing data of the common composite field. The computation circuit generates first intermediate data and second intermediate data of a common composite field by performing computations to the first computing data and the second computing data in the common composite field. The third affine transform circuit transforms the first intermediate data into first computed data of the first Galois field. The fourth affine transform circuit transforms the second intermediate data into second computed data of the second Galois field.

Abstract: A memory device includes a physically unclonable function (PUF) unit, a controller and a memory array. The PUF unit is used to provide a random bit pool. The controller is coupled to the PUF unit and is used to extract a random bit sequence from the random bit pool. The controller includes a masking engine. The masking engine is used to perform a key derivation function to stretch the extracted random bit sequence and to mask an input signal. The memory array is coupled to the masking engine and is used to store according to the masked input signal.

Abstract: An electronic system includes a first circuit and a second circuit. The first circuit includes a first activation unit and a first functional unit. The first activation unit receives a first challenge string, generates a first response string according to the first challenge string and a first key, and outputs the first response string. The first functional unit performs first designated function. The second circuit includes a second activation unit and a second functional unit. The second activation unit sends the first challenge string to the first circuit during a first activation operation, and determines whether the first activation operation passes certification or not according to the first challenge string, the first response string and the first key. The second functional unit performs second designated function when the first activation operation is determined to have passed the certification.

Abstract: A function chip enabling method and a chip using the same. The function circuit enabling method is applicable to a chip including a function circuit, and includes steps of: receiving an enabling code, performing an operation on the enabling code according to a first key of a non-symmetric operation to generate a decrypted enabling code; comparing the decrypted enabling code with a predetermined enabling code to generate an enable signal to enable the function circuit. A second key corresponding to the first key of the non-symmetric operation is not stored in the chip.

Abstract: A method of convolutional decoding with a memory-based Viterbi decoder employs the property of a trace-back path; that is, the similarity between two consecutive trace-back paths becomes higher as the data error rate goes down. Therefore, the method of the invention saves the previous trace-back path into a register, and as soon as the current trace-back path is found to be the same as the previous one, the demanded path is obtained. After that, the memory read operations will stop, thereby reducing the power consumption caused by memory read operations. Prior to path trace-back, the path prediction can be executed by utilizing the property that the minimum path metric and the path are consecutive. The invention reduces the number of memory access operations and power consumption by employing the mechanisms of path matching and path prediction.

Abstract: An algorithm for a memory-based Viterbi decoder is disclosed in the invention, which employs the property of a trace-back path; that is, the similarity between two consecutive trace-back paths becomes higher as the data error rate goes down. Therefore, the algorithm of the invention is to save the previous trace-back path into a register, and as soon as the current trace-back path is found to be the same as the previous one, the demanded path is obtained. After that, the memory read operations will stop, and thus the power consumption made by the memory read operations would be largely reduced. Besides, before the path trace-back, the path prediction can be executed by utilizing the property that the minimum path metric and the path are consecutive. In conclusion, the invention is capable of reducing the number of memory access operations and the power consumption by employing the mechanisms of path matching and path prediction.