Abstract: A driving circuit is provided, including first to second output stage circuits that output, respectively, first and second voltages of a first polarity. The driving circuit further includes a first switch having a first terminal receiving the first voltage from the first output stage circuit and a second terminal coupled to a first output channel through a switching circuit, and a second switch having a first terminal receiving the second voltage from the second output stage circuit and a second terminal coupled to a second output channel through the switching circuit. The driving circuit further includes a first charge sharing circuit having a first terminal coupled to the first output channel and a second terminal coupled to the second output channel. The first charge sharing circuit is turned on to provide charge sharing between the first output channel and the second output channel.

Abstract: An output buffer is provided, which including an input circuit, output circuits, a first multiplexer, a second multiplexer and a demultiplexer. The input circuit is for generating a first control signal and a second control signal according to a feedback signal and an input signal. Each output circuit is controlled by a first gate signal and a second gate signal to provide a corresponding one of output signals. The first multiplexer is for providing the first control signal and the second control signal to one of the output circuits as the first gate signal and the second gate signal, respectively. The second multiplexer is for providing a first reference voltage and a second reference voltage as the first gate signal and the second gate signal, respectively, to other of the output circuits. The demultiplexer is for providing one of the output signals as the feedback signal.

Abstract: A source driver including an output buffer and a feedback circuit is provided. The output buffer includes an input stage circuit, an output stage circuit, a rising control circuit, and a falling control circuit. The input stage circuit correspondingly generates a first gate control voltage and a second gate control voltage according to an input voltage and a first feedback voltage. The output stage circuit correspondingly generates an output voltage according to the first gate control voltage and the second gate control voltage. The feedback circuit generates and outputs the first feedback voltage corresponding to the output voltage to the input stage circuit. The rising control circuit and the falling control circuit compare the input voltage with the first feedback voltage, and pull down (or pull up) the first gate control voltage and the second gate control voltage according to the comparison result.

Abstract: A source driver including an output buffer and a feedback circuit is provided. The output buffer includes an input stage circuit, an output stage circuit, a rising control circuit, and a falling control circuit. The input stage circuit correspondingly generates a first gate control voltage and a second gate control voltage according to an input voltage and a first feedback voltage. The output stage circuit correspondingly generates an output voltage according to the first gate control voltage and the second gate control voltage. The feedback circuit generates and outputs the first feedback voltage corresponding to the output voltage to the input stage circuit. The rising control circuit and the falling control circuit compare the input voltage with the first feedback voltage, and pull down (or pull up) the first gate control voltage and the second gate control voltage according to the comparison result.

Abstract: An output buffer and an operation method thereof are provided. The output buffer includes an input stage circuit, an output stage circuit, a rising control circuit, and a falling control circuit. The input stage circuit correspondingly generates a first gate control voltage and a second gate control voltage according to an input voltage of the output buffer. The output stage circuit correspondingly generates an output voltage of the output buffer according to the first gate control voltage and a second gate control voltage. When the output voltage is to be pulled up, the rising control circuit pulls down the first gate control voltage and the second gate control voltage during a first transient period. When the output voltage is to be pulled down, the falling control circuit pulls up the first gate control voltage and the second gate control voltage during a second transient period.

Abstract: A source driver and an operation method thereof are provided. The source driver includes an output buffer, a feedback switch, and a feedback voltage generating circuit. The output buffer receives the input voltage and produces an output voltage. The first terminal and the second terminal of the feedback switch are respectively coupled to the input terminal and the output terminal of the output buffer. During an overdrive period, the feedback switch is turned off, and the feedback voltage generating circuit outputs a feedback voltage to the output buffer. The feedback voltage is lower than the output voltage when the input voltage is in a rising mode. The feedback voltage is higher than the output voltage when the input voltage is in a falling mode. During a normal driving period, the feedback switch is turned on, and the feedback voltage generating circuit does not output the feedback voltage.

Abstract: A current mirror circuit, receiving an input current and outputting a plurality of mirroring currents, comprising: a first transistor, wherein a control terminal and a first terminal of the first transistor are connected to a first mirroring current of the input current; at least one second transistor, wherein a control terminal and a first terminal of the at least one second transistor are connected to the at least one second mirroring current of the input current; and a plurality of third transistors, outputting the plurality of mirroring currents from first terminals of the plurality of third transistors, wherein control terminals of the plurality of third transistors are connected to control terminals of the first transistor and the at least one second transistor. The first transistor, the at least one second transistor and the plurality of third transistors are identical.

Abstract: A current mirror circuit, receiving an input current and outputting a plurality of mirroring currents, comprising: a first transistor, wherein a control terminal and a first terminal of the first transistor are connected to a first mirroring current of the input current; at least one second transistor, wherein a control terminal and a first terminal of the at least one second transistor are connected to the at least one second mirroring current of the input current; and a plurality of third transistors, outputting the plurality of mirroring currents from first terminals of the plurality of third transistors, wherein control terminals of the plurality of third transistors are connected to control terminals of the first transistor and the at least one second transistor. The first transistor, the at least one second transistor and the plurality of third transistors are identical.