Patents by Inventor Chia-Chu Liu
Chia-Chu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9793268Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.Type: GrantFiled: January 24, 2014Date of Patent: October 17, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Hao Su, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
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Patent number: 9766545Abstract: A method for forming a pattern on a substrate is described. The method includes providing a substrate, forming a photosensitive layer over the substrate, exposing the photosensitive layer to a first exposure energy through a first mask, exposing the photosensitive layer to a second exposure energy through a second mask, baking the photosensitive layer, and developing the exposed photosensitive layer. The photosensitive layer includes a polymer that turns soluble to a developer solution, at least one photo-acid generator (PAG), and at least one photo-base generator (PBG). A portion of the layer exposed to the second exposure energy overlaps with a portion exposed to the first exposure energy.Type: GrantFiled: July 24, 2015Date of Patent: September 19, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ya Hui Chang, Chia-Chu Liu
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Patent number: 9748107Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.Type: GrantFiled: October 23, 2015Date of Patent: August 29, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Chun Lo, Min-Hung Cheng, Hsiao-Wei Su, Jeng-Shiun Ho, Ching-Che Tsai, Cheng-Cheng Kuo, Hua-Tai Lin, Chia-Chu Liu, Kuei-Shun Chen
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Patent number: 9711420Abstract: A method includes processing a first silicon wafer using a first focus condition, the first silicon wafer comprising: a first test pattern and a second test pattern, the first test pattern and the second test pattern being different. The method further includes determining a first critical dimension for the first test pattern, determining a second critical dimension for the second test pattern, determining a delta focus value based on the first critical dimension and the second critical dimension, and processing a second silicon wafer with a second focus condition, the second focus condition based on the delta focus value.Type: GrantFiled: March 14, 2016Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yuan-Yen Lo, Chia-Chu Liu, Ming-Jhih Kuo
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Patent number: 9607835Abstract: A transistor including a gate structure with a first portion and a second portion; the first and second portions each have a first edge and an opposing second edge that are substantially collinear. The gate structure also includes an offset portion interposing the first portion and the second portion. The offset portion has a third edge and an opposing fourth edge. The third edge and the fourth edge are non-collinear with the first and second edges of the first and second portions of the gate structure. For example, the offset portion is offset or shifted from the first and second portions.Type: GrantFiled: June 12, 2015Date of Patent: March 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chu Liu, Min-Chang Liang, Mu-Chi Chiang, Kuei-Shun Chen
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Publication number: 20160365428Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.Type: ApplicationFiled: August 29, 2016Publication date: December 15, 2016Inventors: Chia-Chu LIU, Kuei-Shun CHEN, Chiang MU-CHI, Chao-Cheng CHEN
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Patent number: 9507904Abstract: A circuit layout method comprises inputting layout data into a circuit layout system. The layout data represents a plurality of patterns in a plurality of cells. Each pattern of the plurality of patterns has a plurality of runs, ends, and corners. The method also comprises specifying a plurality of G1-rule criteria. The method further comprises reviewing a representation of G0-space and G0 rule violations for each cell of the plurality of cells. The method additionally comprises inputting an adjustment to the layout data. The method also comprises reviewing a representation of adjusted cell edge spacings, and selecting to output a final layout.Type: GrantFiled: April 22, 2014Date of Patent: November 29, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chu Liu, Kuei Shun Chen
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Patent number: 9466528Abstract: A method of making a structure includes forming a first supporting member over a substrate, the first supporting member comprising a first material and having a first width defined along a reference plane. The method further includes forming a second supporting member over the substrate, the second supporting member having a second width defined along the reference plane, and the first supporting member and the second supporting member being separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region being from 5 to 30 times the second width.Type: GrantFiled: October 6, 2014Date of Patent: October 11, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chu Liu, Yi-Shien Mor, Kuei-Shun Chen, Yu Lun Liu, Han-Hsun Chang, Shiao-Chian Yeh
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Patent number: 9431513Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.Type: GrantFiled: September 29, 2014Date of Patent: August 30, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chu Liu, Kuei-Shun Chen, Chiang Mu-Chi, Chao-Cheng Chen
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Patent number: 9366969Abstract: System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.Type: GrantFiled: June 21, 2013Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chu Liu, Kuei Shun Chen, Norman Chen, Vencent Chang, Chin-Hsiang Lin
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Publication number: 20160093715Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.Type: ApplicationFiled: September 29, 2014Publication date: March 31, 2016Inventors: Chia-Chu Liu, Kuei-Shun Chen, Chiang Mu-Chi, Chao-Cheng Chen
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Patent number: 9281205Abstract: A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer.Type: GrantFiled: January 6, 2014Date of Patent: March 8, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chu Liu, Kuei-Shun Chen, Shang-Wern Chang, Chih-Yang Yeh
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Patent number: 9274414Abstract: A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.Type: GrantFiled: December 3, 2014Date of Patent: March 1, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lun Liu, Chia-Chu Liu, Kuei-Shun Chen, Chung-Ming Wang, Chie-Chieh Lin
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Publication number: 20160042964Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.Type: ApplicationFiled: October 23, 2015Publication date: February 11, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzu-Chun LO, Min-Hung CHENG, Hsiao-Wei SU, Jeng-Shiun HO, Ching-Che TSAI, Cheng-Cheng KUO, Hua-Tai LIN, Chia-Chu LIU, Kuei-Shun CHEN
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Publication number: 20150357460Abstract: A transistor including a gate structure with a first portion and a second portion; the first and second portions each have a first edge and an opposing second edge that are substantially collinear. The gate structure also includes an offset portion interposing the first portion and the second portion. The offset portion has a third edge and an opposing fourth edge. The third edge and the fourth edge are non-collinear with the first and second edges of the first and second portions of the gate structure. For example, the offset portion is offset or shifted from the first and second portions.Type: ApplicationFiled: June 12, 2015Publication date: December 10, 2015Inventors: Chia-Chu Liu, Min-Chang Liang, Mu-Chi Chiang, Kuei-Shun Chen
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Publication number: 20150331324Abstract: A method for forming a pattern on a substrate is described. The method includes providing a substrate, forming a photosensitive layer over the substrate, exposing the photosensitive layer to a first exposure energy through a first mask, exposing the photosensitive layer to a second exposure energy through a second mask, baking the photosensitive layer, and developing the exposed photosensitive layer. The photosensitive layer includes a polymer that turns soluble to a developer solution, at least one photo-acid generator (PAG), and at least one photo-base generator (PBG). A portion of the layer exposed to the second exposure energy overlaps with a portion exposed to the first exposure energy.Type: ApplicationFiled: July 24, 2015Publication date: November 19, 2015Inventors: Ya Hui Chang, Chia-Chu Liu
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Patent number: 9184101Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.Type: GrantFiled: March 11, 2013Date of Patent: November 10, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Chun Lo, Min-Hung Cheng, Hsiao-Wei Su, Jeng-Shiun Ho, Ching-Che Tsai, Cheng-Cheng Kuo, Hua-Tai Lin, Chia-Chu Liu, Kuei-Shun Chen
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Publication number: 20150318367Abstract: Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a substrate having a first active region, a second active region, and an insulating region separating the first and the second active regions. The structure further includes a vertical gate structure extending over the first and the second active regions and the insulating region, and a horizontal gate structure extending over the insulating region between the first and the second active regions.Type: ApplicationFiled: June 26, 2015Publication date: November 5, 2015Inventors: Harry Hak-Lay Chuang, Bao-Ru Young, Kuei Shun Chen, Cheng-Cheng Kuo, Chia-Chu Liu, Tsung-Chieh Tsai, Yuh-Jier Mii
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Patent number: 9129974Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.Type: GrantFiled: August 28, 2014Date of Patent: September 8, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Wen Hsieh, Chi-Kang Chang, Chia-Chu Liu, Meng-Wei Chen, Kuei-Shun Chen
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Publication number: 20150214226Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.Type: ApplicationFiled: January 24, 2014Publication date: July 30, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Hao SU, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen